Vaibbhav Taraate

eBook, PDF

Advanced HDL Synthesis and SOC Prototyping (eBook, PDF)

RTL Design Using Verilog

Beschreibung

Explains SOC architecture and micro-architecture design with case studies

Covers practical scenarios and issues, helpful to both students and professionals

Discusses systems design and testing scenarios using modern FPGAs

Technische Details

• Geräte: PC
• ohne Kopierschutz
• Größe: 18.27MB

Barrierefreiheit

• Text-to-Speech

Autor

Vaibbhav Taraate is an Entrepreneur and Mentor at "Semiconductor Training @ Rs.1". He holds a BE (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology Bombay (IIT Bombay) in 1999. He has over 15 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

Produktdetails

• Verlag: Springer Nature Singapore
• Seitenzahl: 307
• Erscheinungstermin: 15. Dezember 2018
• Englisch
• ISBN-13: 9789811087769
• Artikelnr.: 54762623