Manoj Sachdev, José Pineda de Gyvez

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (eBook, PDF)

• Format: PDF

Produktbeschreibung

Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts.

The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hardto develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.

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Produktdetails

• Verlag: Springer US
• Seitenzahl: 328
• Erscheinungstermin: 4. Juni 2007
• Englisch
• ISBN-13: 9780387465470
• Artikelnr.: 37287302

Autorenporträt

Manoj Sachdev, University of Waterloo, West Ontario, Canada / José Pineda de Gyvez, Philips Research Laboratories and Eindhoven University of Technology, Eindhoven, The Netherlands

Inhaltsangabe

Functional and Parametric Defect Models.- Digital CMOS Fault Modeling.- Defects in Logic Circuits and their Test Implications.- Testing Defects and Parametric Variations in RAMs.- Defect-Oriented Analog Testing.- Yield Engineering.- Conclusion.