. Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework;
. Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-level optimizations;
. Logic synthesis for greater resilience against soft errors, which improves reliability using moderate overhead in area and performance;
. Test-generation and test-compaction methods aimed at probabilistic faults in logic circuits that facilitate accurate and efficient post-manufacture measurement of soft-error susceptibility.
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