Donald G. Bailey

Design for Embedded Image Processing on FPGAs (eBook, PDF)

• Format: PDF

Produktbeschreibung

Design for Embedded Image Processing on FPGAs Bridge the gap between software and hardware with this foundational design reference Field-programmable gate arrays (FPGAs) are integrated circuits designed so that configuration can take place. Circuits of this kind play an integral role in processing images, with FPGAs increasingly embedded in digital cameras and other devices that produce visual data outputs for subsequent realization and compression. These uses of FPGAs require specific design processes designed to mediate smoothly between hardware and processing algorithm. Design for Embedded Image Processing on FPGAs provides a comprehensive overview of these processes and their applications in embedded image processing. Beginning with an overview of image processing and its core principles, this book discusses specific design and computation techniques, with a smooth progression from the foundations of the field to its advanced principles. Readers of the second edition of Design for Embedded Image Processing on FPGAs will also find: * Detailed discussion of image processing techniques including point operations, histogram operations, linear transformations, and more * New chapters covering Deep Learning algorithms and Image and Video Coding * Example applications throughout to ground principles and demonstrate techniques Design for Embedded Image Processing on FPGAs is ideal for engineers and academics working in the field of Image Processing, as well as graduate students studying Embedded Systems Engineering, Image Processing, Digital Design, and related fields.

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Produktdetails

• Verlag: Jossey-Bass
• Seitenzahl: 496
• Erscheinungstermin: 8. August 2023
• Englisch
• ISBN-13: 9781119819806
• Artikelnr.: 68600246

Autorenporträt

Donald G. Bailey, PhD, is Professor of Imaging Systems in the Department of Mechanical and Electrical Engineering, Massey University, New Zealand. He is an internationally recognized expert on FPGA technology in image processing and has published widely on FPGAs and related subjects.

Inhaltsangabe

Preface xiii

Acknowledgments xix

About the Companion Website xxi

1 Image Processing 1

1.1 Basic Definitions 1

1.2 Image Formation 3

1.2.1 Optics 3

1.2.2 Colour 5

1.3 Image Processing Operations 6

1.4 Real-time Image Processing 8

1.5 Embedded Image Processing 9

1.6 Computer Architecture 10

1.7 Parallelism 11

1.7.1 Temporal or Task Parallelism 12

1.7.2 Spatial or Data Parallelism 13

1.7.3 Logical Parallelism 14

1.7.4 Stream Processing 14

1.8 Summary 15

References 16

2 Field-programmable Gate Arrays 19

2.1 Hardware Architecture of FPGAs 19

2.1.1 Logic 21

2.1.2 DSP Blocks 22

2.1.3 Memory 23

2.1.4 Embedded CPU 23

2.1.5 Interconnect 24

2.1.6 Input and Output 24

2.1.7 Clocking 26

2.1.8 Configuration 26

2.1.9 FPGAs vs. ASICs 27

2.2 Programming FPGAs 28

2.2.1 Register Transfer Level 30

2.2.2 Hardware Description Languages 32

2.2.3 High-level Synthesis 33

2.3 FPGAs and Image Processing 38

2.3.1 Choosing an FPGA or Development Board 39

2.4 Summary 40

References 41

3 Design Process 45

3.1 Problem Specification 45

3.2 Algorithm Development 47

3.2.1 Algorithm Development Process 47

3.2.2 Algorithm Structure 48

3.2.3 FPGA Development Issues 51

3.3 Architecture Selection 51

3.3.1 System Architecture 52

3.3.2 Partitioning Between Hardware and Software 53

3.3.3 Computational Architecture 55

3.4 System Implementation 60

3.4.1 Mapping to FPGA Resources 60

3.4.2 Algorithm Mapping Issues 62

3.5 Testing and Debugging 63

3.5.1 Design 63

3.5.2 Implementation 64

3.5.3 Common Implementation Bugs 64

3.5.4 Timing 66

3.5.5 System Debugging 68

3.5.6 Algorithm Tuning 70

3.5.7 In-field Diagnosis 71

3.6 Summary 72

References 73

4 Design Constraints 77

4.1 Timing Constraints 77

4.1.1 Low-level Pipelining 78

4.1.2 Process Synchronisation 80

4.1.3 Synchronising Between Clock Domains 82

4.1.4 I/O Constraints 83

4.2 Memory Bandwidth Constraints 84

4.2.1 Memory Architectures 84

4.2.2 Caching 86

4.2.3 Row Buffering 87

4.3 Resource Constraints 88

4.3.1 Bit-serial Computation 89

4.3.2 Resource Multiplexing 89

4.3.3 Arbitration 92

4.3.4 Resource Controllers 94

4.3.5 Reconfigurability 95

4.4 Power Constraints 97

4.5 Performance Metrics 98

4.5.1 Speed 99

4.5.2 Resources 99

4.5.3 Power 99

4.5.4 Cost 100

4.5.5 Application Metrics 100

4.6 Summary 101

References 102

5 Computational Techniques 105

5.1 Number Systems 105

5.1.1 Binary Integers 105

5.1.2 Residue Systems 106

5.1.3 Redundant Representations 107

5.1.4 Fixed-point Numbers 107

5.1.5 Floating-point Numbers 108

5.1.6 Logarithmic Number System 110

5.1.7 Posit Numbers 110

5.2 Elementary Functions 111

5.2.1 Square Root 111

5.2.2 Trigonometric Functions 112

5.2.3 Linear CORDIC 116

5.2.4 Hyperbolic Functions 117

5.2.5 Logarithms and Exponentials 118<