Suman Lata Tripathi, Sobhit Saxena, Sanjeet K. Sinha, Govind S. Patel

Digital VLSI Design and Simulation with Verilog (eBook, ePUB)

• Format: ePub

Produktbeschreibung

Master digital design with VLSI and Verilog using this up-to-date and comprehensive resource from leaders in the field Digital VLSI Design Problems and Solution with Verilog delivers an expertly crafted treatment of the fundamental concepts of digital design and digital design verification with Verilog HDL. The book includes the foundational knowledge that is crucial for beginners to grasp, along with more advanced coverage suitable for research students working in the area of VLSI design. Including digital design information from the switch level to FPGA-based implementation using hardware description language (HDL), the distinguished authors have created a one-stop resource for anyone in the field of VLSI design. Through eleven insightful chapters, you ll learn the concepts behind digital circuit design, including combinational and sequential circuit design fundamentals based on Boolean algebra. You ll also discover comprehensive treatments of topics like logic functionality of complex digital circuits with Verilog, using software simulators like ISim of Xilinx. The distinguished authors have included additional topics as well, like: * A discussion of programming techniques in Verilog, including gate level modeling, model instantiation, dataflow modeling, and behavioral modeling * A treatment of programmable and reconfigurable devices, including logic synthesis, introduction of PLDs, and the basics of FPGA architecture * An introduction to System Verilog, including its distinct features and a comparison of Verilog with System Verilog * A project based on Verilog HDLs, with real-time examples implemented using Verilog code on an FPGA board Perfect for undergraduate and graduate students in electronics engineering and computer science engineering, Digital VLSI Design Problems and Solution with Verilogalso has a place on the bookshelves of academic researchers and private industry professionals in these fields.

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Produktdetails

• Verlag: John Wiley & Sons
• Seitenzahl: 224
• Erscheinungstermin: 15. Dezember 2021
• Englisch
• ISBN-13: 9781119778080
• Artikelnr.: 63205167

Autorenporträt

Suman Lata Tripathi is Professor of VLSI Design at Lovely Professional University, India. She is a senior member of the IEEE and received her PhD in microelectronics and VLSI Design from Motilal Nehru National Institute of Technology, Allahabad, India. Sobhit Saxena is Associate Professor of VLSI Design at Lovely Professional University, India. He received his PhD from IIT Roorkee, India. Sanjeet K. Sinha, PhD, is Associate Professor of VLSI Design at Lovely Professional University, India. He received his PhD from the National Institute of Technology, Silchar, India. Govind S. Patel, PhD, is Professor of VLSI Design at IIMT College of Engineering, Greater Noida, UP, India. He received his doctorate from Thapar University in Patiala, India.

Inhaltsangabe

Preface xi

About the Authors xiii

1 Combinational Circuit Design 1

1.1 Logic Gates 1

1.1.1 Universal Gate Operation 3

1.1.2 Combinational Logic Circuits 5

1.2 Combinational Logic Circuits Using MSI 6

1.2.1 Adders 6

1.2.2 Multiplexers 12

1.2.3 De-multiplexer 14

1.2.4 Decoders 15

1.2.5 Multiplier 17

1.2.6 Comparators 18

1.2.7 Code Converters 19

1.2.8 Decimal to BCD Encoder 20

Review Questions 21

Multiple Choice Questions 22

Reference 23

2 Sequential Circuit Design 25

2.1 Flip-flops (F/F) 25

2.1.1 S-R F/F 25

2.1.2 D F/F 26

2.1.3 J-K F/F 26

2.1.4 T F/F 28

2.1.5 F/F Excitation Table 29

2.1.6 F/F Characteristic Table 29

2.2 Registers 31

2.2.1 Serial I/P and Serial O/P (SISO) 31

2.2.2 Serial Input and Parallel Output (SIPO) 31

2.2.3 Parallel Input and Parallel Output (PIPO) 32

2.2.4 Parallel Input and Serial Output (PISO) 32

2.3 Counters 33

2.3.1 Synchronous Counter 33

2.3.2 Asynchronous Counter 33

2.3.3 Design of a 3-Bit Synchronous Up-counter 34

2.3.4 Ring Counter 36

2.3.5 Johnson Counter 37

2.4 Finite State Machine (FSM) 37

2.4.1 Mealy and Moore Machine 38

2.4.2 Pattern or Sequence Detector 38

Review Questions 41

Multiple Choice Questions 41

Reference 42

3 Introduction to Verilog HDL 43

3.1 Basics of Verilog HDL 43

3.1.1 Introduction to VLSI 43

3.1.2 Analog and Digital VLSI 43

3.1.3 Machine Language and HDLs 44

3.1.4 Design Methodologies 44

3.1.5 Design Flow 45

3.2 Level of Abstractions and Modeling Concepts 45

3.2.1 Gate Level 45

3.2.2 Dataflow Level 47

3.2.3 Behavioral Level 47

3.2.4 Switch Level 47

3.3 Basics (Lexical) Conventions 47

3.3.1 Comments 47

3.3.2 Whitespace 48

3.3.3 Identifiers 48

3.3.4 Escaped Identifiers 48

3.3.5 Keywords 48

3.3.6 Strings 49

3.3.7 Operators 49

3.3.8 Numbers 49

3.4 Data Types 50

3.4.1 Values 50

3.4.2 Nets 50

3.4.3 Registers 51

3.4.4 Vectors 51

3.4.5 Integer Data Type 51

3.4.6 Real Data Type 51

3.4.7 Time Data Type 52

3.4.8 Arrays 52

3.4.9 Memories 52

3.5 Testbench Concept 53

Multiple Choice Questions 53

References 54

4 Programming Techniques in Verilog I 55

4.1 Programming Techniques in Verilog I 55

4.2 Gate-Level Model of Circuits 55

4.3 Combinational Circuits 57

4.3.1 Adder and Subtractor 57

4.3.2 Multiplexer and De-multiplexer 66

4.3.3 Decoder and Encoder 71

4.3.4 Comparator 75

Review Questions 77

Multiple Choice Questions 77

References 78

5 Programming Techniques in Verilog II 79

5.1 Programming Techniques in Verilog II 79

5.2 Dataflow Model of Circuits 79

5.3 Dataflow Model of Combinational Circuits 80

5.3.1 Adder and Subtractor 80

5.3.2 Multiplexer 82

5.3.3 Decoder 85

5.3.4 Comparator 86

5.4 Testbench 87

5.4.1 Dataflow Model of the Half Adder and Testbench 88

5.4.2 Dataflow Model of the Half Subtractor and Testbench 89

5.4.3 Datafl