Handbook of 3D Integration (eBook, PDF)

Volume 3: 3D Process Technology
Redaktion: Garrou, Philip; Ramm, Peter; Koyanagi, Mitsumasa

• Format: PDF

Produktbeschreibung

Edited by key figures in 3D integration and written by top authors from high-tech companies and renowned research institutions, this book covers the intricate details of 3D process technology. As such, the main focus is on silicon via formation, bonding and debonding, thinning, via reveal and backside processing, both from a technological and a materials science perspective. The last part of the book is concerned with assessing and enhancing the reliability of the 3D integrated devices, which is a prerequisite for the large-scale implementation of this emerging technology. Invaluable reading for materials scientists, semiconductor physicists, and those working in the semiconductor industry, as well as IT and electrical engineers.

---

Dieser Download kann aus rechtlichen Gründen nur mit Rechnungsadresse in A, B, BG, CY, CZ, D, DK, EW, E, FIN, F, GR, HR, H, IRL, I, LT, L, LR, M, NL, PL, P, R, S, SLO, SK ausgeliefert werden.

Produktdetails

• Verlag: Wiley-VCH
• Seitenzahl: 474
• Erscheinungstermin: 22. April 2014
• Englisch
• ISBN-13: 9783527670130
• Artikelnr.: 41117757

Autorenporträt

Philip Garrou is a consultant and expert witness in the field of IC packaging materials and applications, prior to which he was Dir. of Technology and Business Dev. for Dow Chemicals' Electronic Materials business. Dr. Garrou is a Fellow of IEEE and IMAPS and served as President of the IEEE CPMT Society and IMAPS. He has co-authored 3 microelectronics texts and 100+ publications. He is Assoc. Ed. and author of the weekly blog "Insights from the Leading Edge" for Solid State Technology and has co-authored 3DIC reports for both TechSearch and Yole.

Mitsumasa Koyanagi is Professor in New Industry Creation Hatchery Center (NICHe) and Director in GINTI (Global Integration Initiative) at Tohoku University, Japan. After his PhD in electrical engineering he joined the Central Research Laboratory of Hitachi where he was engaged in the research on semiconductor memories. After a three-year stay at the Xerox Palo Alto Research Center in California, USA, he became Professor in the Research Center for Integrated Systems at Hiroshima University, Japan. Mitsumasa Koyanagi received numerous awards, including the IEEE Jun-ichi Nishizawa Medal and the National Medal with Purple Ribbon in Japan.

Peter Ramm is head of the department Heterogeneous System Integration of Fraunhofer EMFT in Munich, Germany, where he is responsible for the key competence "Si Processes, Device and 3D Integration". He received the physics and Dr. rer. nat. degrees from the University of Regensburg and subsequently worked for Siemens in the DRAM facility where he was responsible for the process integration. In 1988 he joined Fraunhofer IFT in Munich, focusing for more than 25 years on 3D integration technologies. Peter Ramm is coauthor of over 100 publications and 24 patents and editor of Wiley´s "Handbook of Wafer Bonding". He received the "Ashman Award 2009" from IMAPS "For Pioneering Work on 3D IC Stacking and Integration".

Inhaltsangabe

3D IC INTEGRATION SINCE 2008
3D IC Nomenclature
Process Standardization
The Introduction of Interposers (2.5D)
The Foundries
Memory
The Assembly and Test Houses
3D IC Application Roadmaps

KEY APPLICATIONS AND MARKED TRENDS FOR 3D INTEGRATION AND INTERPOSER TECHNOLOGIES
Introduction
Advanced Packaging Importance in the Semiconductor Industry is Growing
3D Integration-Focused Activities - The Global IP Landscape
Applications, Technology, and Market Trends

ECONOMIC DRIVERS AND IMPEDIMENTS FOR 2.5D/3D INTEGRATION
3D Performance Advantages
The Economics of Scaling
The Cost of Future Scaling
Cost Remains the Impediment to 2.5D and 3D Product Introduction

INTERPOSER TECHNOLOGY
Definition of 2.5D Interposers
Interposer Drivers and Need
Comparison of Interposer Materials
Silicon Interposers with TSV
Lower Cost Interposers
Interposer Technical and Manufacturing Challenges
Interposer Application Examples
Conclusions

TSV FORMATION OVERVIEW
Introduction
TSV Process Approaches
TSV Fabrication Steps
Yield and Reliability

TSV UNIT PROCESSES AND INTEGRATION
Introduction
TSV Process Overview
TSV Unit Processes
Integration and Co-Optimization of Unit Processes in Via Formation Sequence
Co-Optimization of Unit Processes in Backside Processing and Via-Reveal Flow
Integration and Co-Optimization of Unit Processes in Via-Last Flow
Integration with Packaging
Electrical Characterization of TSVs
Conclusions

TSV FORMATION AT ASET
Introduction
Via-Last TSV for Both D2D and W2W Processes in ASET
TSV Process for D2D
TSV Process for W2W
Conclusions

LASER-ASSISTED WAFER PROCESSING: NEW PERSPECTIVES IN THROUGH-SUBSTRATE VIA DRILLING AND REDISTRIBUTION LAYER DEPOSITION
Introduction
Laser Drilling of TSVs
Direct-Write Deposition of Redistribution Layers
Conclusions and Outlook

TEMPORARY BONDING MATERIAL REQUIREMENTS
Introduction
Technology Options
Requirements of a Temporary Bonding Material
Considerations for Successful Processing
Surviving the Backside Process
Debonding

TEMPORARY BONDING AND DEBONDING - AN UPDATE ON MATERIALS AND METHODS
Introduction
Carrier Selection for Temporary Bonding
Selection of Temporary Bonding Adhesives
Bonding and Debonding Processes
Equipment and Process Integration

ZONEBOND®: RECENT DEVELOPMENTS IN TEMPORARY BONDING AND ROOM-TEMPERATURE DEBONDING
Introduction
Thin Wafer Processing
ZoneBOND Room-Temperature Debonding
Conclusions

TEMPORARY BONDING AND DEBONDING AT TOK
Introduction
Zero Newton Technology
Conclusions

THE 3M (TM) WAFER SUPPORT SYSTEM (WSS)
Introduction
System Description
General Advantages
High-Temperature Material Solutions
Process Considerations
Future Directions
Summary

COMPARISON OF TEMPORARY BONDING AND DEBONDING PROCESS FLOWS
Introduction
Studies of Wafer Bonding and Thinning
Backside Processing
Debonding and Cleaning

THINNING, VIA REVEAL, AND BACKSIDE PROCESSING - OVERVIEW
Introduction
Wafer Edge Trimming
Thin Wafer Support Systems
Wafer Thinning
Thin Wafer Backside Processing

BACKSIDE THINNING AND STRESS-RELIEF TECHNIQUES FOR THIN SILICON WAFERS
Introduction
Thin Semiconductor Devices
Wafer Thinning Techniques
Fracture Tests for Thin Silicon Wafers
Comparison of Stress-Relief Techniques for Wafer Backside Thinning
Process Flow for Wafer Thinning and Dicing
Summary and Outlook on 3D Integration

VIA REVEAL AND BACKSIDE PROCESSING
Introduction
Via Reveal and Backside Processing in Via-Middle Process
Backside Processing in Back-Via Process
Backside Processing and Impurity Gettering
Backside Processing for RDL Formation

DICING, GRINDING, AND POLISHING (KIRU KEZURU AND MIGAKU)
Introduction
Grinding and Polishing
Dicing
Summary

OVERVIEW OF BONDING AND ASSEMBLY FOR 3D INTEGRATION
Introduction
Direct, Indirect, and Hybrid Bonding
Requirements for Bonding Process and Materials
Bonding Quality Characterization
Discussion of Specific Bonding and Assembly Technologies
Summary and Conclusions

BONDING AND ASSEMBLY AT TSMC
Introduction
Process Flow
Chip-on-Wafer Stacking
CoW-on-Substrate (CoWoS) Stacking
CoWoS Versus CoCoS
Testing and Known Good Stacks (KGS)
Future Perspectives

TSV PACKAGING DEVELOPMENT AT STATS ChipPAC
Introduction
Development of the 3DTSV Solution for Mobile Platforms
Alternative Approaches and Future Developments

CU-SIO2 HYBRID BONDING
Introduction
Blanket Cu-SiO2 Direct Bonding Principle
Chemical-Mechanical Polishing Parameters
Aligned Bonding
Blanket Metal Direct Bonding Principle
Electrical Characterization
Conclusions

BUMP INTERCONNECT FOR 2:5D AND 3D INTEGRATION
History
C4 Solder Bumps
Copper Pillar Bumps
Cu Bumps
Electromigration

SELF-ASSEMBLY BASED 3D AND HETEROINTEGRATION
Introduction
Self-Assembly Process
Key Parameters of Self-Assembly on Alignment Accuracies
How to Interconnect Self-Assembled Chips to Chips or Wafers
Flip-Chip-to-Wafer 3D Integration
Reconfigured-Wafer-to-Wafer 3D Integration

HIGH-ACCURACY SELF-ALIGNMENT OF THIN SILICON DIES ON PLASMA-PROGRAMMED SURFACES
Introduction
Principle of Fluidic Self-Alignment Process for Thin Dies
Plasma Programming of the Surface
Preparation of Materials for Self-Alignment Experiments
Self-Alignment Experiments
Results of Self-Alignment Experiments
Discussion
Conclusions

CHALLENGES IN 3D FABRICATION
Introduction
High-Volume Manufacturing for 3D Integration
Technology Challenges
Front-Side and Backside Wafer Processes
Bonding and Underfills
Multitier Stacking
Wafer Thinning and Thin Die and Wafer Handling
Strata Packaging and Assembly
Yield Management
Reliability
Cost Management
Future Perspectives

CU TSV STRESS: AVOIDING CU PROTRUSION AND IMPACT ON DEVICES
Introduction
Cu Stress in TSV
Mitigation of Cu Pumping
Impact of TSVs on FEOL Devices

IMPLICATIONS OF STRESS/STRAIN AND METAL CONTAMINATION ON THINNED DIE
Introduction
Impacts of Cu Contamination on Device Reliabilities in Thinned 3DLSI
Impacts of Local Stress and Strain on Device Reliabilities in Thinned 3DLSI

METROLOGY NEEDS FOR 2.5D/3D INTERCONNECTS
Introduction: 2.5D and 3D Reference Flows
TSV Formation
MEOL Metrology
Assembly and Packaging Metrology
Summary

Index