Farzan Jazaeri

Modeling Nanowire and Double-Gate Junctionless Field-Effect Transistors (eBook, PDF)

• Format: PDF

Produktbeschreibung

The first book on the topic, this is a comprehensive introduction to the modeling and design of junctionless field effect transistors (FETs). Beginning with a discussion of the advantages and limitations of the technology, the authors also provide a thorough overview of published analytical models for double-gate and nanowire configurations, before offering a general introduction to the EPFL charge-based model of junctionless FETs. Important features are introduced gradually, including nanowire versus double-gate equivalence, technological design space, junctionless FET performances, short channel effects, transcapacitances, asymmetric operation, thermal noise, interface traps, and the junction FET. Additional features compatible with biosensor applications are also discussed. This is a valuable resource for students and researchers looking to understand more about this new and fast developing field.

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Produktdetails

• Verlag: Cambridge University Press
• Erscheinungstermin: 1. März 2018
• Englisch
• ISBN-13: 9781108557535
• Artikelnr.: 53398813

Autorenporträt

Farzan Jazaeri is a Scientist at the Ecole Polytechnique Fédérale de Lausanne where his research interests focus on semiconductor devices and physics, and particularly the modeling and fabrication of field-effect transistors.

Inhaltsangabe

1. Introduction
2. Review on modeling junctionless FETs
3. The EPFL charge-based model of junctionless field-effect transistors
4. Model driven design - space of junctionless FETs
5. Generalization of the charge based model: accounting for inversion layers
6. Predicted performances of junctionless FETs
7. Short channel effects in symmetric junctionless double-gate FETs
8. Modeling AC operation in symmetric double-gate and nanowire JL FETs
9. Modeling asymmetric operation of double-gate junctionless FETs
10. Modeling noise behavior in junctionless FETs
11. Carrier mobility extraction methodology in JL and inversion mode FETs
12. Revisiting the Junction FET: a junctionless FET with an ¿ gate capacitance
13. Modeling junctionless FET with interface traps targeting biosensor applications
Appendix A. Design - space of twin gate junctionless vertical slit FETs
Appendix B. Transient off-current in junctionless FETs
Appendix C. Derivatives of mobile charge density with respect to VGS and VDS
Appendix D. Global charge density at drain in depletion mode
Appendix E. Global charge density at drain in accumulation mode
Appendix F. The EPFL Junctionless MODEL ver.1.0.