Liliana Andrade, Frederic Rousseau

Multi-Processor System-on-Chip 1 (eBook, PDF)

Architectures

• Format: PDF

Produktbeschreibung

A Multi-Processor System-on-Chip (MPSoC) is the key component for complex applications. These applications put huge pressure on memory, communication devices and computing units. This book, presented in two volumes Architectures and Applications therefore celebrates the 20th anniversary of MPSoC, an interdisciplinary forum that focuses on multi-core and multi-processor hardware and software systems. It is this interdisciplinarity which has led to MPSoC bringing together experts in these fields from around the world, over the last two decades. Multi-Processor System-on-Chip 1 covers the key components of MPSoC: processors, memory, interconnect and interfaces. It describes advance features of these components and technologies to build efficient MPSoC architectures. All the main components are detailed: use of memory and their technology, communication support and consistency, and specific processor architectures for general purposes or for dedicated applications.

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Produktdetails

• Verlag: John Wiley & Sons
• Seitenzahl: 320
• Erscheinungstermin: 12. März 2021
• Englisch
• ISBN-13: 9781119818274
• Artikelnr.: 61336683

Autorenporträt

Liliana Andrade is Associate Professor at TIMA Lab, Universite Grenoble Alpes in France. She received her PhD in Computer Science, Telecommunications and Electronics from Universite Pierre et Marie Curie in 2016. Her research interests include system-level modeling/validation of systems-on-chips, and the acceleration of heterogeneous systems simulation. Frederic Rousseau is Full Professor at TIMA Lab, Universite Grenoble Alpes in France. His research interests concern Multi-Processor Systems-on-Chip design and architecture, prototyping of hardware/software systems including reconfigurable systems and highlevel synthesis for embedded systems.

Inhaltsangabe

Foreword xiii
Ahmed JERRAYA

Acknowledgments xv
Liliana ANDRADE and Frédéric ROUSSEAU

Part 1. Processors 1

Chapter 1. Processors for the Internet of Things 3
Pieter VAN DER WOLF and Yankin TANURHAN

1.1. Introduction 3

1.2. Versatile processors for low-power IoT edge devices 4

1.2.1. Control processing, DSP and machine learning 4

1.2.2. Configurability and extensibility 6

1.3. Machine learning inference 8

1.3.1. Requirements for low/mid-end machine learning inference 10

1.3.2. Processor capabilities for low-power machine learning inference 14

1.3.3. A software library for machine learning inference 17

1.3.4. Example machine learning applications and benchmarks 20

1.4. Conclusion 23

1.5. References 24

Chapter 2. A Qualitative Approach to Many-core Architecture 27
Benoît DUPONT DE DINECHIN

2.1. Introduction 28

2.2. Motivations and context 29

2.2.1. Many-core processors 29

2.2.2. Machine learning inference 30

2.2.3. Application requirements 32

2.3. The MPPA3 many-core processor 34

2.3.1. Global architecture 34

2.3.2. Compute cluster 36

2.3.3. VLIW core 38

2.3.4. Coprocessor 39

2.4. The MPPA3 software environments 42

2.4.1. High-performance computing 42

2.4.2. KaNN code generator 43

2.4.3. High-integrity computing 46

2.5. Conclusion 47

2.6. References 48

Chapter 3. The Plural Many-core Architecture - High Performance at Low Power 53
Ran GINOSAR

3.1. Introduction 54

3.2. Related works 55

3.3. Plural many-core architecture 55

3.4. Plural programming model 56

3.5. Plural hardware scheduler/synchronizer 58

3.6. Plural networks-on-chip 61

3.6.1. Schedule rNoC 61

3.6.2. Shared memory NoC 61

3.7. Hardware and software accelerators for the Plural architecture 62

3.8. Plural system software 63

3.9. Plural software development tools 65

3.10. Matrix multiplication algorithm on the Plural architecture 65

3.11. Conclusion 67

3.12. References 67

Chapter 4. ASIP-Based Multi-Processor Systems for an Efficient Implementation of CNNs 69
Andreas BYTYN, René AHLSDORF and Gerd ASCHEID

4.1. Introduction 70

4.2. Related works 71

4.3. ASIP architecture 74

4.4. Single-core scaling 75

4.5. MPSoC overview 78

4.6. NoC parameter exploration 79

4.7. Summary and conclusion 82

4.8. References 83

Part 2. Memory 85

Chapter 5. Tackling the MPSoC Data Locality Challenge 87
Sven RHEINDT, Akshay SRIVATSA, Oliver LENKE, Lars NOLTE, Thomas WILD and Andreas HERKERSDORF

5.1. Motivation 88

5.2. MPSoC target platform 90

5.3. Related work 91

5.4. Coherence-on-demand: region-based cache coherence 92

5.4.1. RBCC versus global coherence 93

5.4.2. OS extensions for coherence-on-demand 94

5.4.3. Coherency region manager 94

5.4.4. Experimental evaluations 97

5.4.5. RBCC and data placement 99

5.5. Near-memory acceleration 100

5.5.1. Near-memory synchronization accelerator 102

5.5.2. Near-memory queue management accelerator 104

5.5.3. Near-memory graph copy accelerator 107

5.5.4. Near-cache accelerator 110

5.6. The big picture 111

5.7. Conclusion 113

5.8. Acknowledgments 114

5.9. References 114