Multi-Processor System-on-Chip 2 (eBook, PDF)

Applications
Redaktion: Andrade, Liliana; Rousseau, Frederic

• Format: PDF

Produktbeschreibung

A Multi-Processor System-on-Chip (MPSoC) is the key component for complex applications. These applications put huge pressure on memory, communication devices and computing units. This book, presented in two volumes Architectures and Applications therefore celebrates the 20th anniversary of MPSoC, an interdisciplinary forum that focuses on multi-core and multi-processor hardware and software systems. It is this interdisciplinarity which has led to MPSoC bringing together experts in these fields from around the world, over the last two decades. Multi-Processor System-on-Chip 2 covers application-specific MPSoC design, including compilers and architecture exploration. This second volume describes optimization methods, tools to optimize and port specific applications on MPSoC architectures. Details on compilation, power consumption and wireless communication are also presented, as well as examples of modeling frameworks and CAD tools. Explanations of specific platforms for automotive and real-time computing are also included.

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Produktdetails

• Verlag: John Wiley & Sons
• Seitenzahl: 272
• Erscheinungstermin: 31. März 2021
• Englisch
• ISBN-13: 9781119818380
• Artikelnr.: 61690732

Autorenporträt

Liliana Andrade is Associate Professor at TIMA Lab, Université Grenoble Alpes in France. She received her PhD in Computer Science, Telecommunications and Electronics from Université Pierre et Marie Curie in 2016. Her research interests include system-level modeling/validation of systems-on-chips, and the acceleration of heterogeneous systems simulation. Frédéric Rousseau is Full Professor at TIMA Lab, Université Grenoble Alpes in France. His research interests concern Multi-Processor Systems-on-Chip design and architecture, prototyping of hardware/software systems including reconfigurable systems and highlevel synthesis for embedded systems.

Inhaltsangabe

Foreword xi
Ahmed JERRAYA

Acknowledgments xiii
Liliana ANDRADE and Frédéric ROUSSEAU

Part 1. MPSoC for Telecom 1

Chapter 1. From Challenges to Hardware Requirements for Wireless Communications Reaching 6G 3
Stefan A. DAMJANCEVIC, Emil MATUS, Dmitry UTYANSKY, Pieter VAN DER WOLF and Gerhard P. FETTWEIS

1.1. Introduction 4

1.2. Breadth of workloads 6

1.2.1. Vision, trends and applications 6

1.2.2. Standard specifications 8

1.2.3. Outcome of workloads 13

1.3. GFDM algorithm breakdown 14

1.3.1. Equation 15

1.3.2. Dataflow processing graph and matrix representation 15

1.3.3. Pseudo-code 16

1.4. Algorithm precision requirements and considerations 18

1.5. Implementation 21

1.5.1. Implementation considerations 23

1.5.2. Design space exploration 23

1.5.3. Measurements for low-end and high-end use cases 26

1.6. Conclusion 28

1.7. Acknowledgments 29

1.8. References 29

Chapter 2. Towards Tbit/s Wireless Communication Baseband Processing: When Shannon meets Moore 33
Matthias HERRMANN and Norbert WEHN

2.1. Introduction 34

2.2. Role of microelectronics 36

2.3. Towards 1 Tbit/s throughput decoders 37

2.3.1. Turbodecoder 39

2.3.2. LDPC decoder 41

2.3.3. Polar decoder 41

2.4. Conclusion 43

2.5. Acknowledgments 43

2.6. References 43

Part 2. Application-specific MPSoC Architectures 47

Chapter 3. Automation for Industry 4.0 by using Secure LoRaWAN Edge Gateways 49
Marcello COPPOLA and George KORNAROS

3.1. Introduction 50

3.2. Security in IIoT 52

3.3. LoRaWAN security in IIoT 53

3.4. Threatmodel 55

3.4.1. LoRaWAN attack model 55

3.4.2. IIoT node attack model 56

3.5. Trusted boot chain with STM32MP1 57

3.5.1. Trust base of node 57

3.5.2. Trusted firmware inSTM32MP1 57

3.5.3. Trusted execution environments and OP-TEE 58

3.5.4. OP-TEE scheduling considerations 60

3.5.5. OP-TEEmemorymanagement 60

3.5.6. OP-TEE clientAPI 61

3.5.7.TEE internal coreAPI 62

3.5.8. Root and chain of trust 62

3.5.9. Hardware unique key 62

3.5.10. Secure clock 63

3.5.11. Cryptographic operations 63

3.6. LoRaWAN gateway withSTM32MP1 64

3.7. Discussion and future scope 65

3.8. Acknowledgments 66

3.9. References 66

Chapter 4. Accelerating Virtualized Distributed NVMe Storage in Hardware 69
Julian CHESTERFIELD and Michail FLOURIS

4.1. Introduction 70

4.1.1. Virtualization and traditional hypervisors 71

4.1.2. Hyperconverged versus disaggregated cloud architectures 72

4.1.3. NVMe flash storage 74

4.2. Motivation:NVMe storage for the cloud 75

4.2.1. Motivation for a new hypervisor 75

4.2.2. Motivation for accelerating disaggregated storage 76

4.3. Design 77

4.3.1. Optimizing the hypervisor I/O operations 77

4.3.2. Design of accelerated disaggregated storage 80

4.4. Implementation 86

4.4.1. The NexVisor platform 87

4.4.2. Accelerated disaggregated storage 87

4.5. Results 90

4.5.1. Sequential reads 90

4.5.2. Sequentialwrites 90

4.5.3. Sequential reads on one NVMe drive 92

4.5.4. Networkperformance 92

4.6. Conclusion 93

4.7. References 93

Chapter 5. Modular and Open Platform for Future Automotive Co