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This book provides a comprehensive review of the state-of-the-art in the development of new and innovative materials, and of advanced modeling and characterization methods for nanoscale CMOS devices. Leading global industry bodies including the International Technology Roadmap for Semiconductors (ITRS) have created a forecast of performance improvements that will be delivered in the foreseeable future - in the form of a roadmap that will lead to a substantial enlargement in the number of materials, technologies and device architectures used in CMOS devices. This book addresses the field of…mehr
This book provides a comprehensive review of the state-of-the-art in the development of new and innovative materials, and of advanced modeling and characterization methods for nanoscale CMOS devices. Leading global industry bodies including the International Technology Roadmap for Semiconductors (ITRS) have created a forecast of performance improvements that will be delivered in the foreseeable future - in the form of a roadmap that will lead to a substantial enlargement in the number of materials, technologies and device architectures used in CMOS devices. This book addresses the field of materials development, which has been the subject of a major research drive aimed at finding new ways to enhance the performance of semiconductor technologies. It covers three areas that will each have a dramatic impact on the development of future CMOS devices: global and local strained and alternative materials for high speed channels on bulk substrate and insulator; very low access resistance; and various high dielectric constant gate stacks for power scaling. The book also provides information on the most appropriate modeling and simulation methods for electrical properties of advanced MOSFETs, including ballistic transport, gate leakage, atomistic simulation, and compact models for single and multi-gate devices, nanowire and carbon-based FETs. Finally, the book presents an in-depth investigation of the main nanocharacterization techniques that can be used for an accurate determination of transport parameters, interface defects, channel strain as well as RF properties, including capacitance-conductance, improved split C-V, magnetoresistance, charge pumping, low frequency noise, and Raman spectroscopy.
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Autorenporträt
Francis Balestra is Director of the Laboratoire de Physique des Composants - Semiconducteurs (LPCS) at INP Grenoble in France. He has coauthored over 80 publications in international scientific journals and 120 communications at national and international conferences (20 invited papers and review articles).
Inhaltsangabe
Introduction xv F. BALESTRA PART 1. NOVEL MATERIALS FOR NANOSCALE CMOS 1 Chapter 1. Introduction to Part 1 3 D. LEADLEY, A. DOBBIE, V. SHAH and J. PARSONS 1.1. Nanoscale CMOS requirements 3 1.2. The gate stack - high-_ dielectrics 5 1.3. Strained channels 7 1.4. Source-drain contacts 16 1.5. Bibliography 17 Chapter 2. Gate Stacks 23 O. ENGSTRÖM, I. Z. MITROVIC, S. HALL, P. K. HURLEY, K. CHERKAOUI, S. MONAGHAN, H. D. B. GOTTLOB and M. C. LEMME 2.1. Gate-channel coupling in MOSFETs 23 2.2. Properties of dielectrics 24 2.3. Interfaces states and bulk oxide traps 29 2.4. Two ternary compounds: GdSiO and LaSiO 39 2.5. Metal gate technology 50 2.6. Future outlook 56 2.7. Bibliography 58 Chapter 3. Strained Si and Ge Channels 69 D. LEADLEY, A. DOBBIE, M. MYRONOV, V. SHAH and E. PARKER 3.1. Introduction 69 3.2. Relaxation of strained layers 74 3.3. High Ge composition Si1-xGex buffers 83 3.4. Ge channel devices 105 3.5. Acknowledgements 115 3.6. Bibliography 115 Chapter 4. From Thin Si/SiGe Buffers to SSOI 127 S. MANTL and D. BUCA 4.1. Introduction 128 4.2. Nucleation of dislocations 129 4.3. Strain relaxation and strain transfer mechanisms 131 4.4. Overgrowth of strained Si and layer optimization 134 4.5. Characterization of the elastic strain 137 4.6. SSOI wafer fabrication 141 4.7. SSOI as channel material for MOSFET devices 145 4.8. Summary 152 4.9. Bibliography 153 Chapter 5. Introduction to Schottky-Barrier MOS Architectures: Concept, Challenges, Material Engineering and Device Integration 157 E. DUBOIS, G. LARRIEU, R VALENTIN, N. BREIL and F. DANNEVILLE 5.1. Introduction 157 5.2. Challenges associated with the source/drain extrinsic contacts 158 5.3. Extraction of low Schottky barriers 166 5.4. Modulation of Schottky barrier height using low temperature dopant segregation 177 5.5. State-of-the-art device integration 191 5.6. Conclusion 195 5.7. Acknowledgements 197 5.8. Bibliography 197 PART 2. ADVANCED MODELING AND SIMULATION FOR NANO-MOSFETS AND BEYOND-CMOS DEVICES 205 Chapter 6. Introduction to Part 2 207 E. SANGIORGI 6.1. Modeling and simulation approaches for gate current computation 208 6.2. Modeling and simulation approaches for drain current computation 209 6.3. Modeling of end of the roadmap nMOSFET with alternative channel material 209 6.4. NEGF simulations of nanoscale CMOS in the effective mass approximation 210 6.5. Compact models for advanced CMOS devices 211 6.6. Beyond CMOS 211 6.7. Bibliography 212 Chapter 7. Modeling and Simulation Approaches for Gate Current Computation 213 B. MAJKUSIAK, P. PALESTRI, A. SCHENK, A. S. SPINELLI, C. M. COMPAGNONI and M. LUISIER 7.1. Introduction 213 7.2. Calculation of the tunneling probability 216 7.3. Tunneling in nonconventional devices 228 7.4. Trap-assisted tunneling 237 7.5. Models for gate current computation in commercial TCAD 243 7.6. Comparison between modeling approaches 249 7.7. Bibliography 251 Chapter 8. Modeling and Simulation Approaches for Drain Current Computation 259 M. VASICEK, D. ESSENI, C. FIEGNA and T. GRASSER 8.1. Boltzmann transport equation for MOS transistors 260 8.2. Method of moments 262 8.3. Subband macroscopic transport models 276 8.4. Comparison with device-SMC 278 8.5. Conclusions 282 8.6. Bibliography 283 Chapter 9. Modeling of End of the Roadmap nMOSFET with Alternative Channel Material 287 Q. RAFHAY, R. CLERC, G. GHIBAUDO, P. PALESTRI and L. SELMI 9.1. Introduction: replacing silicon as channel material 287 9.2. State-of-the-art in the modeling of alternative channel material devices 290 9.3. Critical analysis of the literature using analytical models 297 9.4. Conclusions 327 9.5. Bibliography 328 Chapter 10. NEGF for 3D Device Simulation of Nanometric Inhomogenities 335 A. MARTINEZ, A. ASENOV and M. PALA 10.1. Introduction 335 10.2. Variabilities for nanoscale CMOS 343 10.3. Full quantum treatment of spatial fluctuations in ultra-scaled devices 361 10.4. Bibliography 377 Chapter 11. Compact Models for Advanced CMOS Devices 381 B. IÑIGUEZ, F. LIME, A. LÁZARO and T. A. FJELDLY 11.1. Introduction 381 11.2. Electrostatics modeling issues 385 11.3. Transport modeling issues 388 11.4. 1D compact models 390 11.5. Ultimate MuGFET modeling issues: ballistic current and quantum confinement 405 11.6. Velocity saturation and channel length modulation modeling 409 11.7. Hydrodynamic transport model 411 11.8. Charge and capacitance modeling 413 11.9. Short-channel effects 420 11.10. RF and noise modeling 434 11.11. Acknowledgements 437 11.12. Bibliography 438 Chapter 12. Beyond CMOS 443 G. IANNACCONE, G. FIORI, S. REGGIANI and M. PALA 12.1. Introduction 443 12.2. Atomistic modeling of carbon-based FETs 444 12.3. Numerical simulation of CNT-FETs 447 12.4. Effective mass modeling of carbon nanotube FETs 451 12.5. CNT versus graphene nanoribbon FETs 459 12.6. Full-quantum treatment of elastic and inelastic scattering in Si and SiC GAA nanowire FETs 461 12.7. Conclusions 467 12.8. Bibliography 468 PART 3. NANOCHARACTERIZATION METHODS 471 Chapter 13. Introduction to Part 3 473 D. FLANDRE Chapter 14. Accurate Determination of Transport Parameters in Sub-65 nm MOS Transistors 475 M. MOUIS and G. GHIBAUDO 14.1. Impact of transport on device performance in the drift-diffusion regime 476 14.2. Standard extraction techniques and their adaptation to short channel transistors 482 14.3. Alternative extraction techniques 518 14.4. Out of equilibrium transport 531 14.5. Conclusions 537 14.6. Bibliography 539 Chapter 15. Characterization of Interface Defects 545 P. HURLEY, O. ENGSTRÖM, D. BAUZA and G. GHIBAUDO 15.1. Characterization using the capacitance-voltage (C-V) response 545 15.2. Characterization using the conductance-voltage (G-V) response 550 15.3. Charge pumping 553 15.4. Low frequency noise 561 15.5. Bibliography 566 Chapter 16. Strain Determination 575 A. O'NEILL, S. OLSEN, P. DOBROSZ, R. AGAIBY and Y. TSANG 16.1. Introduction 575 16.2. Characterization requirements 575 16.3. Characterization techniques 579 16.4. Strain description 592 16.5. Bibliography 598 Chapter 17. Wide Frequency Band Characterization 603 D. FLANDRE, J.-P. RASKIN and V. KILCHYTSKA 17.1. Modified split-CV technique for reliable mobility extraction 604 17.2. Small-signal electrical characterization of FinFETs: impact of access resistances and capacitances 610 17.3. Substrate-related output conductance degradation 619 17.4. Small-signal electrical characterization of Schottky barrier MOSFETs 626 17.5. Bibliography 632 List of Authors 639 Index 649
Introduction xv F. BALESTRA PART 1. NOVEL MATERIALS FOR NANOSCALE CMOS 1 Chapter 1. Introduction to Part 1 3 D. LEADLEY, A. DOBBIE, V. SHAH and J. PARSONS 1.1. Nanoscale CMOS requirements 3 1.2. The gate stack - high-_ dielectrics 5 1.3. Strained channels 7 1.4. Source-drain contacts 16 1.5. Bibliography 17 Chapter 2. Gate Stacks 23 O. ENGSTRÖM, I. Z. MITROVIC, S. HALL, P. K. HURLEY, K. CHERKAOUI, S. MONAGHAN, H. D. B. GOTTLOB and M. C. LEMME 2.1. Gate-channel coupling in MOSFETs 23 2.2. Properties of dielectrics 24 2.3. Interfaces states and bulk oxide traps 29 2.4. Two ternary compounds: GdSiO and LaSiO 39 2.5. Metal gate technology 50 2.6. Future outlook 56 2.7. Bibliography 58 Chapter 3. Strained Si and Ge Channels 69 D. LEADLEY, A. DOBBIE, M. MYRONOV, V. SHAH and E. PARKER 3.1. Introduction 69 3.2. Relaxation of strained layers 74 3.3. High Ge composition Si1-xGex buffers 83 3.4. Ge channel devices 105 3.5. Acknowledgements 115 3.6. Bibliography 115 Chapter 4. From Thin Si/SiGe Buffers to SSOI 127 S. MANTL and D. BUCA 4.1. Introduction 128 4.2. Nucleation of dislocations 129 4.3. Strain relaxation and strain transfer mechanisms 131 4.4. Overgrowth of strained Si and layer optimization 134 4.5. Characterization of the elastic strain 137 4.6. SSOI wafer fabrication 141 4.7. SSOI as channel material for MOSFET devices 145 4.8. Summary 152 4.9. Bibliography 153 Chapter 5. Introduction to Schottky-Barrier MOS Architectures: Concept, Challenges, Material Engineering and Device Integration 157 E. DUBOIS, G. LARRIEU, R VALENTIN, N. BREIL and F. DANNEVILLE 5.1. Introduction 157 5.2. Challenges associated with the source/drain extrinsic contacts 158 5.3. Extraction of low Schottky barriers 166 5.4. Modulation of Schottky barrier height using low temperature dopant segregation 177 5.5. State-of-the-art device integration 191 5.6. Conclusion 195 5.7. Acknowledgements 197 5.8. Bibliography 197 PART 2. ADVANCED MODELING AND SIMULATION FOR NANO-MOSFETS AND BEYOND-CMOS DEVICES 205 Chapter 6. Introduction to Part 2 207 E. SANGIORGI 6.1. Modeling and simulation approaches for gate current computation 208 6.2. Modeling and simulation approaches for drain current computation 209 6.3. Modeling of end of the roadmap nMOSFET with alternative channel material 209 6.4. NEGF simulations of nanoscale CMOS in the effective mass approximation 210 6.5. Compact models for advanced CMOS devices 211 6.6. Beyond CMOS 211 6.7. Bibliography 212 Chapter 7. Modeling and Simulation Approaches for Gate Current Computation 213 B. MAJKUSIAK, P. PALESTRI, A. SCHENK, A. S. SPINELLI, C. M. COMPAGNONI and M. LUISIER 7.1. Introduction 213 7.2. Calculation of the tunneling probability 216 7.3. Tunneling in nonconventional devices 228 7.4. Trap-assisted tunneling 237 7.5. Models for gate current computation in commercial TCAD 243 7.6. Comparison between modeling approaches 249 7.7. Bibliography 251 Chapter 8. Modeling and Simulation Approaches for Drain Current Computation 259 M. VASICEK, D. ESSENI, C. FIEGNA and T. GRASSER 8.1. Boltzmann transport equation for MOS transistors 260 8.2. Method of moments 262 8.3. Subband macroscopic transport models 276 8.4. Comparison with device-SMC 278 8.5. Conclusions 282 8.6. Bibliography 283 Chapter 9. Modeling of End of the Roadmap nMOSFET with Alternative Channel Material 287 Q. RAFHAY, R. CLERC, G. GHIBAUDO, P. PALESTRI and L. SELMI 9.1. Introduction: replacing silicon as channel material 287 9.2. State-of-the-art in the modeling of alternative channel material devices 290 9.3. Critical analysis of the literature using analytical models 297 9.4. Conclusions 327 9.5. Bibliography 328 Chapter 10. NEGF for 3D Device Simulation of Nanometric Inhomogenities 335 A. MARTINEZ, A. ASENOV and M. PALA 10.1. Introduction 335 10.2. Variabilities for nanoscale CMOS 343 10.3. Full quantum treatment of spatial fluctuations in ultra-scaled devices 361 10.4. Bibliography 377 Chapter 11. Compact Models for Advanced CMOS Devices 381 B. IÑIGUEZ, F. LIME, A. LÁZARO and T. A. FJELDLY 11.1. Introduction 381 11.2. Electrostatics modeling issues 385 11.3. Transport modeling issues 388 11.4. 1D compact models 390 11.5. Ultimate MuGFET modeling issues: ballistic current and quantum confinement 405 11.6. Velocity saturation and channel length modulation modeling 409 11.7. Hydrodynamic transport model 411 11.8. Charge and capacitance modeling 413 11.9. Short-channel effects 420 11.10. RF and noise modeling 434 11.11. Acknowledgements 437 11.12. Bibliography 438 Chapter 12. Beyond CMOS 443 G. IANNACCONE, G. FIORI, S. REGGIANI and M. PALA 12.1. Introduction 443 12.2. Atomistic modeling of carbon-based FETs 444 12.3. Numerical simulation of CNT-FETs 447 12.4. Effective mass modeling of carbon nanotube FETs 451 12.5. CNT versus graphene nanoribbon FETs 459 12.6. Full-quantum treatment of elastic and inelastic scattering in Si and SiC GAA nanowire FETs 461 12.7. Conclusions 467 12.8. Bibliography 468 PART 3. NANOCHARACTERIZATION METHODS 471 Chapter 13. Introduction to Part 3 473 D. FLANDRE Chapter 14. Accurate Determination of Transport Parameters in Sub-65 nm MOS Transistors 475 M. MOUIS and G. GHIBAUDO 14.1. Impact of transport on device performance in the drift-diffusion regime 476 14.2. Standard extraction techniques and their adaptation to short channel transistors 482 14.3. Alternative extraction techniques 518 14.4. Out of equilibrium transport 531 14.5. Conclusions 537 14.6. Bibliography 539 Chapter 15. Characterization of Interface Defects 545 P. HURLEY, O. ENGSTRÖM, D. BAUZA and G. GHIBAUDO 15.1. Characterization using the capacitance-voltage (C-V) response 545 15.2. Characterization using the conductance-voltage (G-V) response 550 15.3. Charge pumping 553 15.4. Low frequency noise 561 15.5. Bibliography 566 Chapter 16. Strain Determination 575 A. O'NEILL, S. OLSEN, P. DOBROSZ, R. AGAIBY and Y. TSANG 16.1. Introduction 575 16.2. Characterization requirements 575 16.3. Characterization techniques 579 16.4. Strain description 592 16.5. Bibliography 598 Chapter 17. Wide Frequency Band Characterization 603 D. FLANDRE, J.-P. RASKIN and V. KILCHYTSKA 17.1. Modified split-CV technique for reliable mobility extraction 604 17.2. Small-signal electrical characterization of FinFETs: impact of access resistances and capacitances 610 17.3. Substrate-related output conductance degradation 619 17.4. Small-signal electrical characterization of Schottky barrier MOSFETs 626 17.5. Bibliography 632 List of Authors 639 Index 649
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