Woogeun Rhee, Zhiping Yu

Phase-Locked Loops (eBook, PDF)

System Perspectives and Circuit Design Aspects

• Format: PDF

Produktbeschreibung

Phase-Locked Loops Discover the essential materials for phase-locked loop circuit design, from fundamentals to practical design aspects A phase-locked loop (PLL) is a type of circuit with a range of important applications in telecommunications and computing. It generates an output signal with a controlled relationship to an input signal, such as an oscillator which matches the phases of input and output signals. This is a critical function in coherent communication systems, with the result that the theory and design of these circuits are essential to electronic communications of all kinds. Phase-Locked Loops: System Perspectives and Circuit Design Aspects provides a concise, accessible introduction to PLL design. It introduces readers to the role of PLLs in modern communication systems, the fundamental techniques of phase-lock circuitry, and the possible applications of PLLs in a wide variety of electronic communications contexts. The first book of its kind to incorporate modern architectures and to balance theoretical fundamentals with detailed design insights, this promises to be a must-own text for students and industry professionals. The book also features: * Coverage of PLL basics with insightful analysis and examples tailored for circuit designers * Applications of PLLs for both wireless and wireline systems * Practical circuit design aspects for modern frequency generation, frequency modulation, and clock recovery systems Phase-Locked Loops is essential for graduate students and advanced undergraduates in integrated circuit design, as well researchers and engineers in electrical and computing subjects.

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Produktdetails

• Verlag: For Dummies
• Seitenzahl: 384
• Erscheinungstermin: 22. Dezember 2023
• Englisch
• ISBN-13: 9781119909057
• Artikelnr.: 69861523

Autorenporträt

Woogeun Rhee, PhD, is a Professor at the School of Integrated Circuits, Tsinghua University, Beijing. He has over 25 years of professional career experience in integrated circuit design with nearly 10 years in industry and 16 years in academia. Dr. Rhee is one of a few researchers who made significant contributions to PLL architectures and circuits not only within different careers (academia and industry) but also over different fields (wireless and wireline systems). He is an IEEE Fellow. Zhiping Yu, PhD, is a Professor at the School of Integrated Circuits, Tsinghua University, Beijing. He is an IEEE Life Fellow with over 400 published papers on subjects related to ICCAD, nanoelectronics and RF circuit design.

Inhaltsangabe

Preface xiii
About Authors xv
1 Introduction 1
1.1 Phase-Lock Technique 1
1.2 Key Properties and Applications 2
1.3 Organization and Scope of the Book 6
Part I Phase-Lock Basics 9
2 Linear Model and Loop Dynamics 11
2.1 Linear Model of the PLL 11
2.2 Feedback System 13
2.3 Loop Dynamics of the PLL 16
2.4 Noise Transfer Function 26
2.5 Charge-Pump PLL 29
2.6 Other Design Considerations 39
3 Transient Response 43
3.1 Linear Transient Performance 44
3.2 Nonlinear Transient Performance 52
3.3 Practical Design Aspects 56
Part II System Perspectives 67
4 Frequency and Spectral Purity 69
4.1 Spur Generation and Modulation 69
4.2 Phase Noise and Random Jitter 87
5 Application Aspects 101
5.1 Frequency Synthesis 102
5.2 Clock-and-Data Recovery 112
5.3 Clock Generation 120
5.4 Synchronization 127
Part III Building Circuits 135
6 PhaseDetector 137
6.1 Non-Memory Phase Detectors 137
6.2 Phase-Frequency Detector 142
6.3 Charge Pump 149
7 Voltage-Controlled Oscillator 165
7.1 Oscillator Basics 166
7.2 LC VCO 175
7.3 RING VCO 190
7.4 Relaxation VCO 201
8 FrequencyDivider 209
8.1 Basic Operation 209
8.2 Circuit Design Considerations 219
8.3 Other Topologies 229
Part IV PLL Architectures 237
9 Fractional-N PLL 239
9.1 Fractional-N Frequency Synthesis 239
9.2 Frequency Synthesis with Delta-Sigma Modulation 249
9.3 Quantization Noise Reduction Methods 271
9.4 Frequency Modulation by Fractional-N PLL 278
10 Digital-Intensive PLL 287
10.1 DPLL with Linear TDC 288
10.2 DPLL with 1-Bit TDC 304
10.3 Hybrid PLL 315
11 Clock-and-Data Recovery PLL 325
11.1 Loop Dynamics Considerations for CDR 325
11.2 CDR PLL Architectures Based on Phase Detection 329
11.3 Frequency Acquisition 340
11.4 DLL-assisted CDR Architectures 344
11.5 Open-Loop CDR Architectures 351
References 355
Index 359