Planar Double-Gate Transistor will mainly focus on SOI CMOS transistors, fully depleted with double independent planar Gates (Independent Planar Double Gates Transistors: IPDGT), a potential candidate for the sub-32 nm technological nodes as planned by the current ITRS Roadmap.
The book topics are mainly focusing on:
- Detailed description of specific processes that allow the optimization of the CMOS IPDGT device
- CMOS IPDGT modeling, both compact and physical models are presented
- Device characterization
- Design of innovating cells (SRAM cells, basic digital & analog functions) with the objectives to improve the level of integration and the robustness to variability as well as the power consumption optimization, using the degree of freedom introduced by the independent gates.
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