An in-depth presentation of preliminary concepts makes the book self-contained. Based on this foundation major design problems are targeted. In particular, a complete tool flow for Synthesis for Testability of SystemC descriptions is presented. The resulting circuits are completely testable and test pattern generation in polynomial time is possible. Verification issues are covered in even more detail. A whole new paradigm for formal design verification is suggested. This is based upon design understanding, the automatic generation of properties and powerful tool support for debugging failures. All these new techniques are empirically evaluated and experimental results are provided.
As a result, an enhanced design flow is created that provides more automation (i.e. better usability) and reduces the probability of introducing conceptual errors (i.e. higher robustness).
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"The authors, Gorschwin Fey and Rolf Drechsler, have identified several deficiencies in the design steps and manual fault diagnosis and have proposed a number of methods to alleviate the problems. ... The book is a useful contribution to circuit design productivity and reliability." (Nirode C. Mohanty, Zentralblatt MATH, Vol. 1198, 2010)