Behnam Ghavami, Mohsen Raji

Soft Error Reliability of VLSI Circuits (eBook, PDF)

Analysis and Mitigation Techniques

• Format: PDF

Produktbeschreibung

This book is intended for readers who are interested in the design of robust and reliable electronic digital systems. The authors cover emerging trends in design of today's reliable electronic systems which are applicable to safety-critical applications, such as automotive or healthcare electronic systems. The emphasis is on modeling approaches and algorithms for analysis and mitigation of soft errors in nano-scale CMOS digital circuits, using techniques that are the cornerstone of Computer Aided Design (CAD) of reliable VLSI circuits. The authors introduce software tools for analysis and mitigation of soft errors in electronic systems, which can be integrated easily with design flows. In addition to discussing soft error aware analysis techniques for combinational logic, the authors also describe new soft error mitigation strategies targeting commercial digital circuits. Coverage includes novel Soft Error Rate (SER) analysis techniques such as process variation aware SER estimationand GPU accelerated SER analysis techniques, in addition to SER reduction methods such as gate sizing and logic restructuring based SER techniques.

• Provides an accessible, comprehensive introduction to soft errors;
• Describes an easy to follow procedure for modeling, analysis, and estimation of soft error rate of digital circuits;
• Includes state-of-the art soft error aware CAD algorithms;
• Describes practical soft error aware synthesis techniques for commercial large-scale VLSI designs.

---

Dieser Download kann aus rechtlichen Gründen nur mit Rechnungsadresse in A, B, BG, CY, CZ, D, DK, EW, E, FIN, F, GR, HR, H, IRL, I, LT, L, LR, M, NL, PL, P, R, S, SLO, SK ausgeliefert werden.

Produktdetails

• Verlag: Springer International Publishing
• Seitenzahl: 114
• Erscheinungstermin: 13. Oktober 2020
• Englisch
• ISBN-13: 9783030516109
• Artikelnr.: 61344376

Autorenporträt

Behnam Ghavami was born in Esfarayen, Iran. He received his Ph.D. degree in computer engineering from Amirkabir University of Technology, Tehran, Iran. He has been serving as a Faculty Member with the Computer Engineering Department, Shahid Bahonar University of Kerman, since 2010, where he is currently Tenured Associate Professor. He teaches courses in design of digital systems, computer architecture, FPGA design, and reliable circuit design. He has supervised or co-supervised about 20 graduate students. He has published over 100 refereed papers. His research interests include the design automation of digital systems, robust logic designs, and FPGA-based design. He is currently an Associate Editor of the Journal of Electronic Testing-Springer and Microelectronics Journal-Elsevier. He has a decade of industry experience, including working on FPGA systems in industry.

Mohsen Raji received his Ph.D. degree in computer engineering from Amirkabir University of Technology, Tehran,Iran. He has been serving as an Assistant Professor in School of Electrical and Computer Engineering, Shiraz University, Shiraz, Iran, since 2015. He teaches courses such as VLSI systems design, microprocessors, embedded systems, fault tolerant system design. He has supervised or co-supervised about 10 graduate students and published over 30 refereed papers. He is serving as an associated editor of Iranian Journal of Science and Technology, Transactions of Electrical Engineering. His current research interests include dependable computing, reliable and robust logic designs, design automation of digital systems, and embedded systems.

Inhaltsangabe

Introduction: Soft Error Modeling.- Soft Error Rate Estimation of VLSI circuits.- Process Variation Aware Soft Error Rate Estimation Method for Integrated Circuits.- GPU-Accelerated Soft Error Rate Analysis of Large-scale Integrated Circuits.- FPGA Hardware Acceleration of Soft Error Rate Estimation of Digital Circuits.- Soft Error Tolerant Circuit Design using Partitioning-based Gate Sizing.- Resynthesize Technique for Soft Error Tolerant Design of Combinational Circuits.