This book provides readers with tools for variation-aware design methodologies and computer-aided design (CAD) of VLSI systems, in the presence of process variations at the nanometer scale. It presents the latest developments for modeling and analysis, with a focus on statistical interconnect modeling, statistical parasitic extractions, statistical full-chip leakage and dynamic power analysis considering spatial correlations, statistical analysis and modeling for large global interconnects and analog/mixed-signal circuits.
- Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits;
- Helps chip designers understand the potential and limitations of their design tools, improving their design productivity;
- Presents analysis of each algorithm with practical applications in the context of real circuit design;
- Includes numerical examples for the quantitative analysis and evaluation of algorithms presented.
- Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits;
- Helps chip designers understand the potential and limitations of their design tools, improving their design productivity;
- Presents analysis of each algorithmwith practical applications in the context of real circuit design;
- Includes numerical examples for the quantitative analysis and evaluation of algorithms presented.
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