Substrate Noise Coupling in RFICs reports silicon measurements, new test and noise isolation structures as well as calibration of a design flow used in the design and debug phases of RFICs. A design guide is articulated to be used by RFIC designers to maximize signal isolation and optimize chip floor plan, power and ground domains. Industrial examples of RFICs are given as demonstration vehicles to validate the proposed techniques. Some emphasis is put on the design of on-chip spiral inductors and the impact of the substrate on their performance. To our knowledge, this is the first title devoted to the topic of substrate noise coupling in RFICs as part of a large SoC.
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