Sie sind bereits eingeloggt. Klicken Sie auf 2. tolino select Abo, um fortzufahren.
Bitte loggen Sie sich zunächst in Ihr Kundenkonto ein oder registrieren Sie sich bei bücher.de, um das eBook-Abo tolino select nutzen zu können.
SystemVerilog for Verification, Second Edition provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. It also reviews SystemVerilog 3.0 topics such as interfaces and data types. This second edition contains a new chapter that covers programs and interfaces as…mehr
SystemVerilog for Verification, Second Edition provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. It also reviews SystemVerilog 3.0 topics such as interfaces and data types.
This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch. This edition also includes a new chapter that covers “Interfacing to C” and many new and improved examples and explanations.
For hardware engineers, the book has several chapters with detailed explanations of Object Oriented Programming based on years of teaching OOP to hundreds of students. For software engineers, there is a wealth of information on testbenches, multithreaded code, and interfacing to hardware designs. The reader only needs to know the Verilog 1995 standard.
"The complete book that covers verification concepts and use of system verilog in Verification, taking your from an easy start to advanced concepts with ease.
Paul D. Franzon, Alumni Distinguished Professor of ECE, North Carolina State University"
Chris Spear has been working in the ASIC design and verification field for 30 years. He started his career with Digital Equipment Corporation (DEC) as a / CAD Engineer on DECsim, connecting the first Zycad box ever sold, and then a hardware Verification engineer for the VAX 8600, and a hardware behavioral simulation accelerator. He then moved on to Cadence where he was an Application Engineer for Verilog-XL, followed by a stint at Viewlogic. Chris is currently employed at Synopsys Inc. as a Verification Consultant, a title he created a dozen years ago. He has authored the first and second editions of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features. Chris earned a BSEE from Cornell University in 1981. In his spare time, Chris enjoys road biking in the mountains and traveling with his wife. Greg Tumbush has been designing and verifying ASICs and FPGAs for 13 years. After working as a researcher in the Air Force Research Labs (AFRL) he moved to beautiful Colorado to work with Astek Corp as a Lead ASIC Design Engineer. He then began a 6 year career with Starkey Labs, AMI Semiconductor, and ON Semiconductor where he was an early adopter of SystemC and SystemVerilog. In 2008, Greg left ON Semiconductor to form Tumbush Enterprises, LLC where he has been consulting clients in the areas of design, verification, and backend to ensure first pass success. He is also a part time Instructor at the University of Colorado, Colorado Springs where he teaches senior and graduate level digital design and verification courses. He has numerous publications which can be viewed at www.tumbush.com. Greg earned a Ph.D. from the University of Cincinnati in 1998.
Inhaltsangabe
1. Verification Guidelines.- 1.1 The Verification Process.- 1.2 The Verification Methodology Manual.- 1.3 Basic Testbench Functionality.- 1.4 Directed Testing.- 1.5 Methodology Basics.- 1.6 Constrained-Random Stimulus.- 1.7 What Should You Randomize?.- 1.8 Functional Coverage.- 1.9 Testbench Components.- 1.10 Layered Testbench.- 1.11 Building a Layered Testbench.- 1.12 Simulation Environment Phases.- 1.13 Maximum Code Reuse.- 1.14 Testbench Performance.- 1.15 Conclusion.- 2. Data Types.- 2.1 Built-in Data Types.- 2.2 Fixed-Size Arrays.- 2.3 Dynamic Arrays.- 2.4 Queues.- 2.5 Associative Arrays.- 2.6 Linked Lists.- 2.7 Array Methods.- 2.8 Choosing a Storage Type.- 2.9 Creating New Types with typedef.- 2.10 Creating User-Defined Structures.- 2.11 Type conversion.- 2.12 Enumerated Types.- 2.13 Constants.- 2.14 Strings.- 2.15 Expression Width.- 2.16 Conclusion.- 3. Procedural Statements and Routines.- 3.1 Procedural Statements.- 3.2 Tasks, Functions, and Void Functions.- 3.3 Task and Function Overview.- 3.4 Routine Arguments.- 3.5 Returning from a Routine.- 3.6 Local Data Storage.- 3.7 Time Values.- 3.8 Conclusion.- 4. Connecting The Testbench and Design.- 4.1 Separating the Testbench and Design.- 4.2 The Interface Construct.- 4.3 Stimulus Timing.- 4.4 Interface Driving and Sampling.- 4.5 Connecting It All Together.- 4.6 Top-Level Scope.- 4.7 Program — Module Interactions.- 4.8 SystemVerilog Assertions.- 4.9 The Four-Port ATM Router.- 4.10 The ref Port Direction.- 4.11 The End of Simulation.- 4.12 Directed Test for the LC3 Fetch Block.- 4.13 Conclusion.- 5. Basic Oop.- 5.1 Introduction.- 5.2 Think of Nouns, not Verbs.- 5.3 Your First Class.- 5.4 Where to Define a Class.- 5.5 OOP Terminology.- 5.6 Creating New Objects.- 5.7 Object Deallocation.- 5.8 Using Objects.- 5.9Static Variables vs. Global Variables.- 5.10 Class Methods.- 5.11 Defining Methods Outside of the Class.- 5.12 Scoping Rules.- 5.13 Using One Class Inside Another.- 5.14 Understanding Dynamic Objects.- 5.15 Copying Objects.- 5.16 Public vs. Local.- 5.17 Straying Off Course.- 5.18 Building a Testbench.- 5.19 Conclusion.- 6. Randomization.- 6.1 Introduction.- 6.2 What to Randomize.- 6.3 Randomization in SystemVerilog.- 6.4 Constraint Details.- 6.5 Solution Probabilities.- 6.6 Controlling Multiple Constraint Blocks.- 6.7 Valid Constraints.- 6.8 In-line Constraints.- 6.9 The pre_randomize and post_randomize Functions.- 6.10 Random Number Functions.- 6.11 Constraints Tips and Techniques.- 6.12 Common Randomization Problems.- 6.13 Iterative and Array Constraints.- 6.14 Atomic Stimulus Generation vs. Scenario Generation.- 6.15 Random Control.- 6.16 Random Number Generators.- 6.17 Random Device Configuration.- 6.18 Conclusion.- 7. Threads and Interprocess Communication.- 7.1 Working with Threads.- 7.2 Disabling Threads.- 7.3 Interprocess Communication.- 7.4 Events.- 7.5 Semaphores.- 7.6 Mailboxes.- 7..- 7.7 Building a Testbench with Threads and IPC.- 7.8 Conclusion.- 8. Advanced Oop and Testbench Guidelines.- 8.1 Introduction to Inheritance.- 8.2 Blueprint Pattern.- 8.3 Downcasting and Virtual Methods.- 8.4 Composition, Inheritance, and Alternatives.- 8.5 Copying an Object.- 8.6 Abstract Classes and Pure Virtual Methods.- 8.7 Callbacks.- 8.8 Parameterized Classes.- 8.9 Conclusion.- 9. Functional Coverage.- 9.1 Coverage Types.- 9.2 Functional Coverage Strategies.- 9.3 Simple Functional Coverage Example.- 9.4 Anatomy of a Cover Group.- 9.5 Triggering a Cover Group.- 9.6 Data Sampling.- 9.7 Cross Coverage.- 9.8 Generic Cover Groups.- 9.9 Coverage Options.- 9.10 Analyzing CoverageData.- 9.11 Measuring Coverage Statistics During Simulation.- 9.12 Conclusion.- 10. Advanced Interfaces.- 10.1 Virtual Interfaces with the ATM Router.- 10.2 Connecting to Multiple Design Configurations.- 10.3 Procedural Code in an Interface.- 10.4 Conclusion.- 11. A Complete Systemverilog Testbench.- 11.1 Design Blocks.- 11.2 Testbench Blocks.- 11.3 Alternate Tests.- 11.4 Conclusion.- 12. Interfacing With C.- 12.1 Passing Simple Values.- 12.2 Connecting to a Simple C Routine.- 12.3 Connecting to C++.- 12.4 Simple Array Sharing.- 12.5 Open arrays.- 12.6 Sharing Composite Types.- 12.7 Pure and Context Imported Methods.- 12.8 Communicating from C to System Verilog.- 12.9 Connecting Other Languages.- 12.10 Conclusion.- References.
Verification Guidelines.- Data Types.- Procedural Statements and Routines.- Connecting the Testbench and Design.- Basic OOP.- Randomization.- Threads and Interprocess Communication.- Advanced OOP and Testbench Guidelines.- Functional Coverage.- Advanced Interfaces.- A Complete SystemVerilog Testbench.- Interfacing with C/C++.
1. Verification Guidelines.- 1.1 The Verification Process.- 1.2 The Verification Methodology Manual.- 1.3 Basic Testbench Functionality.- 1.4 Directed Testing.- 1.5 Methodology Basics.- 1.6 Constrained-Random Stimulus.- 1.7 What Should You Randomize?.- 1.8 Functional Coverage.- 1.9 Testbench Components.- 1.10 Layered Testbench.- 1.11 Building a Layered Testbench.- 1.12 Simulation Environment Phases.- 1.13 Maximum Code Reuse.- 1.14 Testbench Performance.- 1.15 Conclusion.- 2. Data Types.- 2.1 Built-in Data Types.- 2.2 Fixed-Size Arrays.- 2.3 Dynamic Arrays.- 2.4 Queues.- 2.5 Associative Arrays.- 2.6 Linked Lists.- 2.7 Array Methods.- 2.8 Choosing a Storage Type.- 2.9 Creating New Types with typedef.- 2.10 Creating User-Defined Structures.- 2.11 Type conversion.- 2.12 Enumerated Types.- 2.13 Constants.- 2.14 Strings.- 2.15 Expression Width.- 2.16 Conclusion.- 3. Procedural Statements and Routines.- 3.1 Procedural Statements.- 3.2 Tasks, Functions, and Void Functions.- 3.3 Task and Function Overview.- 3.4 Routine Arguments.- 3.5 Returning from a Routine.- 3.6 Local Data Storage.- 3.7 Time Values.- 3.8 Conclusion.- 4. Connecting The Testbench and Design.- 4.1 Separating the Testbench and Design.- 4.2 The Interface Construct.- 4.3 Stimulus Timing.- 4.4 Interface Driving and Sampling.- 4.5 Connecting It All Together.- 4.6 Top-Level Scope.- 4.7 Program — Module Interactions.- 4.8 SystemVerilog Assertions.- 4.9 The Four-Port ATM Router.- 4.10 The ref Port Direction.- 4.11 The End of Simulation.- 4.12 Directed Test for the LC3 Fetch Block.- 4.13 Conclusion.- 5. Basic Oop.- 5.1 Introduction.- 5.2 Think of Nouns, not Verbs.- 5.3 Your First Class.- 5.4 Where to Define a Class.- 5.5 OOP Terminology.- 5.6 Creating New Objects.- 5.7 Object Deallocation.- 5.8 Using Objects.- 5.9Static Variables vs. Global Variables.- 5.10 Class Methods.- 5.11 Defining Methods Outside of the Class.- 5.12 Scoping Rules.- 5.13 Using One Class Inside Another.- 5.14 Understanding Dynamic Objects.- 5.15 Copying Objects.- 5.16 Public vs. Local.- 5.17 Straying Off Course.- 5.18 Building a Testbench.- 5.19 Conclusion.- 6. Randomization.- 6.1 Introduction.- 6.2 What to Randomize.- 6.3 Randomization in SystemVerilog.- 6.4 Constraint Details.- 6.5 Solution Probabilities.- 6.6 Controlling Multiple Constraint Blocks.- 6.7 Valid Constraints.- 6.8 In-line Constraints.- 6.9 The pre_randomize and post_randomize Functions.- 6.10 Random Number Functions.- 6.11 Constraints Tips and Techniques.- 6.12 Common Randomization Problems.- 6.13 Iterative and Array Constraints.- 6.14 Atomic Stimulus Generation vs. Scenario Generation.- 6.15 Random Control.- 6.16 Random Number Generators.- 6.17 Random Device Configuration.- 6.18 Conclusion.- 7. Threads and Interprocess Communication.- 7.1 Working with Threads.- 7.2 Disabling Threads.- 7.3 Interprocess Communication.- 7.4 Events.- 7.5 Semaphores.- 7.6 Mailboxes.- 7..- 7.7 Building a Testbench with Threads and IPC.- 7.8 Conclusion.- 8. Advanced Oop and Testbench Guidelines.- 8.1 Introduction to Inheritance.- 8.2 Blueprint Pattern.- 8.3 Downcasting and Virtual Methods.- 8.4 Composition, Inheritance, and Alternatives.- 8.5 Copying an Object.- 8.6 Abstract Classes and Pure Virtual Methods.- 8.7 Callbacks.- 8.8 Parameterized Classes.- 8.9 Conclusion.- 9. Functional Coverage.- 9.1 Coverage Types.- 9.2 Functional Coverage Strategies.- 9.3 Simple Functional Coverage Example.- 9.4 Anatomy of a Cover Group.- 9.5 Triggering a Cover Group.- 9.6 Data Sampling.- 9.7 Cross Coverage.- 9.8 Generic Cover Groups.- 9.9 Coverage Options.- 9.10 Analyzing CoverageData.- 9.11 Measuring Coverage Statistics During Simulation.- 9.12 Conclusion.- 10. Advanced Interfaces.- 10.1 Virtual Interfaces with the ATM Router.- 10.2 Connecting to Multiple Design Configurations.- 10.3 Procedural Code in an Interface.- 10.4 Conclusion.- 11. A Complete Systemverilog Testbench.- 11.1 Design Blocks.- 11.2 Testbench Blocks.- 11.3 Alternate Tests.- 11.4 Conclusion.- 12. Interfacing With C.- 12.1 Passing Simple Values.- 12.2 Connecting to a Simple C Routine.- 12.3 Connecting to C++.- 12.4 Simple Array Sharing.- 12.5 Open arrays.- 12.6 Sharing Composite Types.- 12.7 Pure and Context Imported Methods.- 12.8 Communicating from C to System Verilog.- 12.9 Connecting Other Languages.- 12.10 Conclusion.- References.
Verification Guidelines.- Data Types.- Procedural Statements and Routines.- Connecting the Testbench and Design.- Basic OOP.- Randomization.- Threads and Interprocess Communication.- Advanced OOP and Testbench Guidelines.- Functional Coverage.- Advanced Interfaces.- A Complete SystemVerilog Testbench.- Interfacing with C/C++.
Es gelten unsere Allgemeinen Geschäftsbedingungen: www.buecher.de/agb
Impressum
www.buecher.de ist ein Shop der buecher.de GmbH & Co. KG i.I. Bürgermeister-Wegele-Str. 12, 86167 Augsburg Amtsgericht Augsburg HRA 13309
