Peter J. Ashenden

The Designer's Guide to VHDL (eBook, ePUB)

• Format: ePub

Produktbeschreibung

VHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. The Designer's Guide to VHDL has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008.

• First comprehensive book on VHDL to incorporate all new features of VHDL-2008, the latest release of the VHDL standard
• Helps readers get up to speed quickly with new features of the new standard
• Presents a structured guide to the modeling facilities offered by VHDL
• Shows how VHDL functions to help design digital systems
• Includes extensive case studies and source code used to develop testbenches and case study examples
• Helps readers gain maximum facility with VHDL for design of digital systems

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Produktdetails

• Verlag: Elsevier Science & Techn.
• Seitenzahl: 936
• Erscheinungstermin: 7. Oktober 2010
• Englisch
• ISBN-13: 9780080568850
• Artikelnr.: 38120841

Autorenporträt

Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.

Inhaltsangabe

1. Fundamental Concepts 2. Scalar Data Types and Operations 3. Sequential Statements 4. Composite Data Types and Operations 5. Basic Modeling Constructs 6. Case Study: A Pipelined Complex Multiplier Accumulator 7. Subprograms 8. Packages and Use Clauses 9. Aliases 10. External Names in Testbenches 11. Properties and Assertion-Based Design 12. Resolved Signals 13. Generics 14. Components and Configurations 15. Generate Statements 16. Access Types and Abstract Data Types 17. Files and Input/Output 18. Case Study: Queuing Networks 19. Attributes and Groups 20. Design for Synthesis 21. Case Study: System Design using the Gumnut Core 22. Miscellaneous Topics

Appendix A. Standard Packages B. Related Standards C. VHDL Syntax D. Differences Among VHDL Versions E. Answers to Exercises