Sie sind bereits eingeloggt. Klicken Sie auf 2. tolino select Abo, um fortzufahren.
Bitte loggen Sie sich zunächst in Ihr Kundenkonto ein oder registrieren Sie sich bei bücher.de, um das eBook-Abo tolino select nutzen zu können.
This book discusses the advantages and challenges of Body-Biasing for integrated circuits and systems, together with the deployment of the design infrastructure needed to generate this Body-Bias voltage. These new design solutions enable state of the art energy efficiency and system flexibility for the latest applications, such as Internet of Things and 5G communications. Provides readers with a single-source reference to Body-Biasing Techniques for FDSOI Circuits and Systems; | Describes integrated circuit design techniques specific to deep submicron Ultra Thin Body and Box…mehr
This book discusses the advantages and challenges of Body-Biasing for integrated circuits and systems, together with the deployment of the design infrastructure needed to generate this Body-Bias voltage. These new design solutions enable state of the art energy efficiency and system flexibility for the latest applications, such as Internet of Things and 5G communications.
Provides readers with a single-source reference to Body-Biasing Techniques for FDSOI Circuits and Systems;
Describes integrated circuit design techniques specific to deep submicron Ultra Thin Body and Box Fully-Depleted Silicon on Insulator CMOS technology;
Presents the first coherent collection of FDSOI specific design techniques, for applications ranging from analog, RF, mmW to SRAM design, embedded power management and energy efficient digital design.
Dieser Download kann aus rechtlichen Gründen nur mit Rechnungsadresse in A, B, BG, CY, CZ, D, DK, EW, E, FIN, F, GR, HR, H, IRL, I, LT, L, LR, M, NL, PL, P, R, S, SLO, SK ausgeliefert werden.
Sylvain CLERC (M'99) received the Engineering Degree in Digital System Architecture from Grenoble National Polytechnical Institute in 1993. From 1995 to 1999 he was with Dolphin Integration, now Dolphin Design, Meylan, France, working on memory generator design and automated layout. In 1999, he joined STMicroelectronics, Crolles, France, in Technology Design Platform group. He was responsible for standard cell design and Silicon qualification. From 2006 to 2016 he was in a team in charge of radiation hardening and silicon IPs qualification for space and terrestrial environments. He is now working in Digital Design Flow Methodology team. His current research domain is Safety and Energy Efficient circuit design. Thierry DI GILIO was born in 1978 in Marseille, France. He received his his M.Sc in Physic and Modelling Of complex Systems from University of Provence, France in 2002. In 2006, he obtained his PhD degree in nano-electronic from University of Provence. During 3 years, heworked at Sofradir (Veurey-Voroise, France) as a consultant, and designed several Readout Circuits for cooled infrared detector applications. In 2011 he joined STMicroelectronics Central R&D (in Crolles, France) to design embedded power management circuits for digital and RF SoCs including the development of embedded boby biasing solutions for FDSOI technologies. He is now in charge of Power Management IP design within Imaging Product group. Andreia Cathelin (M'04, SM'11) is a Technology R&D Fellow at STMicroelectronics, Crolles France. She started electrical engineering studies at the Polytechnic Institute of Bucarest, Romania and graduated with MS from the Institut Supérieur d'Electronique du Nord (ISEN), Lille, France in 1994. In 1998 and 2013 respectively, she received PhD and "habilitation à diriger des recherches" (French highest academic degree) from the Université de Lille 1, France. Since 1998, she has been with STMicroelectronics, Crolles, France. Her focus areas are in the design of RF/mmW/THz and ultra-low-power circuits and systems. She is leading and driving advanced R&D research topics, also in collaboration with major research teams from Universities worldwide. She is as well one of the pioneers worldwide in FD-SOI CMOS design. Andreia has had numerous responsibilities inside the IEEE community since more than 10 years. At ISSCC, she has been the RF sub-committee chair from 2012 to 2015, and since 2016 is the Forums Chair and member of the Executive Committee. She has been the ESSCIRC-ESSDERC Steering Committee Chair from 2015 to 2017 and is the Technical Program Chair for ESSCIRC2020. She has served different positions on the Technical Program Committees of VLSI Symposium on Circuits from 2010 till 2016, and is now member of its Executive Committee. She has been an elected member of the IEEE SSCS Adcom for the term January 2015 to December 2017 and for the 2020-2022 term, and is an activemember of the IEEE SSCS Women in Circuits group. Andreia has authored or co-authored 130+ technical papers and 7 book chapters and has filed more than 25 patents. She is a co-recipient of the ISSCC 2012 Jan Van Vessem Award for Outstanding European Paper and of the ISSCC 2013 Jack Kilby Award for Outstanding Student Paper. She is as well the winner of the 2012 STMicroelectronics Technology Council Innovation Prize, for having introduced on the company's roadmap the integrated CMOS THz technology for imaging applications.
Inhaltsangabe
Introduction.- What for Body Bias.- Design Examples: system and signal path.- Body Bias Voltage Generation and Infrastructure.- Conclusion.
