Paul Jespers

The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits (eBook, PDF)

The semi-empirical and compact model approaches

• Format: PDF

Produktbeschreibung

How to determine transistor sizes and currents when the supply voltages of analog CMOS circuits do not exceed 1.2V and transistors operate in weak, moderate or strong inversion? The g_m/I_D methodology offers a solution provided a reference transconductance over drain current ratio is available. The reference may be the result of measurements carried out on real physical transistors or advanced models. The reference may also take advantage of a compact model. In The g_m/I_D Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits, we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com allow redoing the tests.

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Produktdetails

• Verlag: Springer US
• Seitenzahl: 171
• Erscheinungstermin: 1. Dezember 2009
• Englisch
• ISBN-13: 9780387471013
• Artikelnr.: 37287453

Autorenporträt

Dr. Paul Jespers is Professor Emeritus at UCL, Louvain-la-Neuf, Belgium, and has been visiting professor at Stanford ('67-'69) and UC Berkeley ('90-'91). He has co-authored several books, and in 2001 published "Integrated Digital-to-Analog and Analog-to-Digital Converters" which was published by Wiley (ISBN 0-19-856446-5)

Inhaltsangabe

Preface. Notations. Chapter 1. Sizing the Intrinsic Gain Stage. Chapter 2. The Charge Sheet Model revisited. Chapter 3. Graphical interpretation of the Charge Sheet Model. Chapter 4. Compact modeling. Chapter 5. The real transistor. Chapter 6. The real Intrinsic Gain Stage. Chapter 7. The common gate configuration. Chapter 8. Sizing the Miller Op. Amp. Annex 1. How to utilize the C.D. ROM data. Annex 2. The MATLAB toolbox. Annex 3. Temperature and Mismatch, from C.S.M. to E.K.V. Annex 4. E.K.V. intrinsic capacitance models. Bibliography. Index.