Ivan S. Kourtev, Baris Taskin, Eby G. Friedman

Timing Optimization Through Clock Skew Scheduling (eBook, PDF)

• Format: PDF

Produktbeschreibung

History of the Book The last three decades have witnessed an explosive development in - tegrated circuit fabrication technologies. The complexities of current CMOS circuits are reaching beyond the 65 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the succe- ful design and implementation of thousands of high performance, large scale integrated circuits. This book (a research monograph) originated from a body of doctoral d- sertationresearchcompletedbythe?rstauthorattheUniversityofRochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution network in large scale, high performance digital synchronous circuits and particularly, on algorithmsfornon-zero clockskewscheduling.Duringthedevelopmentofthis research, it became clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical developments in this area have been slow to reach the designers’ desktops. The second edition of the book is enhanced by the body of doctoral dissertation research completed by the second author at the University of Pittsburgh from 2000 to 2005 under the supervision of Prof.

Produktdetails

• Verlag: Springer US
• Erscheinungstermin: 16. November 2008
• Englisch
• ISBN-13: 9780387710563
• Artikelnr.: 37288109

Autorenporträt

Professor Dr. Eby Friedman, Department of Electrical & Computer Engineering, University of Rochester, Rochester, New York 14627-0231, USA.

Inhaltsangabe

VLSI Systems.- Signal Delay in VLSI Systems.- Timing Properties of Synchronous Systems.- Clock Skew Scheduling and Clock Tree Synthesis.- Clock Skew Scheduling of Level-Sensitive Circuits.- Clock Skew Scheduling for Improved Reliability.- Delay Insertion and Clock Skew Scheduling.- Practical Considerations.- Clock Skew Scheduling in Rotary Clocking Technology.- Experimental Results.

---

1. Introduction.- 2. VLSI Systems.- 2.1 Signal Representation.- 2.2 Synchronous VLSI Systems.- 2.3 The VLSI Design Process.- 2.4 Summary.- 3. Signal Delay In Vlsi Systems.- 3.1 Delay Metrics.- 3.2 Devices and Interconnections.- 4. Timing Properties Of Synchronous Systems.- 4.1 Storage Elements.- 4.2 Latches.- 4.3 Parameters of Latches.- 4.4 Flip-Flops.- 4.5 Parameters of Flip-Flops.- 4.6 The Clock Signal.- 4.7 Single-Phase Path with Flip-Flops.- 4.8 Single-Phase Path with Latches.- 4.9 A Final Note.- 5. Clock Scheduling and Clock Tree Synthesis.- 5.1 Background.- 5.2 Definitions and Graphical Model.- 5.3 Clock Scheduling.- 5.4 Structure of the Clock Distribution Network.- 5.5 Solution of the Clock Tree Synthesis Problem.- 5.6 Software Implementation.- 6. Clock Scheduling For Improved Reliability.- 6.1 Problem Formulation.- 6.2 Derivation of the QP Algorithm.- 7. Practical Considerations.- 7.1 Computational Analysis.- 7.2 Unconstrained Basis Skews.- 7.3 I/O Registers and Target Delays.- 8. Experimental Results.- 8.1 Description of Computer Implementation.- 8.2 Graphical Illustrations of Results.- 9. Conclusions.- 10. Future Directions.- 10.1 Algorithmic Enhancements.- 10.2 Practical Considerations.- References.- Appendices.- A- Numerical Illustration of Algorithms.- A.1 Algorithm LMCS-1.- A.2 Algorithm LMCS-2.- A.3 Algorithm CSD.- B- Glossary of Terms.- C- Graphical Illustration of Results.- About the Authors.