Sie sind bereits eingeloggt. Klicken Sie auf 2. tolino select Abo, um fortzufahren.
Bitte loggen Sie sich zunächst in Ihr Kundenkonto ein oder registrieren Sie sich bei bücher.de, um das eBook-Abo tolino select nutzen zu können.
VLSI 2010 Annual Symposium will present extended versions of the best papers presented in ISVLSI 2010 conference. The areas covered by the papers will include among others: Emerging Trends in VLSI, Nanoelectronics, Molecular, Biological and Quantum Computing. MEMS, VLSI Circuits and Systems, Field-programmable and Reconfigurable Systems, System Level Design, System-on-a-Chip Design, Application-Specific Low Power, VLSI System Design, System Issues in Complexity, Low Power, Heat Dissipation, Power Awareness in VLSI Design, Test and Verification, Mixed-Signal Design and Analysis,…mehr
VLSI 2010 Annual Symposium will present extended versions of the best papers presented in ISVLSI 2010 conference. The areas covered by the papers will include among others: Emerging Trends in VLSI, Nanoelectronics, Molecular, Biological and Quantum Computing. MEMS, VLSI Circuits and Systems, Field-programmable and Reconfigurable Systems, System Level Design, System-on-a-Chip Design, Application-Specific Low Power, VLSI System Design, System Issues in Complexity, Low Power, Heat Dissipation, Power Awareness in VLSI Design, Test and Verification, Mixed-Signal Design and Analysis, Electrical/Packaging Co-Design, Physical Design, Intellectual property creating and sharing.
1. Intelligent NOC Hotspot Prediction.- 2. Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model.- 3. Trust Management Through Hardware Means: Design Concerns and Optimizations.- 4. MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures.- 5. 2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.- 6. Adaptive Task Migration Policies for Thermal Control in MPSoCs.- 7. A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning.- 8. A Scalable Bandwidth Aware Architecture for Connected Component Labelling.- 9. The SATURN Approach to SysML-based HW/SW Codesign.- 10. Mapping Embedded Applications on MPSoC - The MNEMEE approach.- 11. The MOSART Mapping Optimisation for Scalable Multi-core ARchiTecture.- 12. XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation.- 13. Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing.- 14. SUT-RNS Forward and Reverse Converters.- 15. Off-Chip SDRAM Access Through Spidergon STNoC.- 16. Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore.- 17. FPGA Startup through Sequential Partial and Dynamic Reconfiguration.- 18. Two Dimensional Dynamic Multigrained Reconfigurable Hardware.- 19. System Level Design for Embedded Reconfigurable Systems using MORPHEUS Platform.- 20. New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems through Dynamic and Partial Reconfiguration: The RAMPSoC Approach.
1. Intelligent NOC Hotspot Prediction.- 2. Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model.- 3. Trust Management Through Hardware Means: Design Concerns and Optimizations.- 4. MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures.- 5. 2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.- 6. Adaptive Task Migration Policies for Thermal Control in MPSoCs.- 7. A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning.- 8. A Scalable Bandwidth Aware Architecture for Connected Component Labelling.- 9. The SATURN Approach to SysML-based HW/SW Codesign.- 10. Mapping Embedded Applications on MPSoC - The MNEMEE approach.- 11. The MOSART Mapping Optimisation for Scalable Multi-core ARchiTecture.- 12. XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation.- 13. Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing.- 14. SUT-RNS Forward and Reverse Converters.- 15. Off-Chip SDRAM Access Through Spidergon STNoC.- 16. Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore.- 17. FPGA Startup through Sequential Partial and Dynamic Reconfiguration.- 18. Two Dimensional Dynamic Multigrained Reconfigurable Hardware.- 19. System Level Design for Embedded Reconfigurable Systems using MORPHEUS Platform.- 20. New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems through Dynamic and Partial Reconfiguration: The RAMPSoC Approach.
1. Intelligent NOC Hotspot Prediction.- 2. Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model.- 3. Trust Management Through Hardware Means: Design Concerns and Optimizations.- 4. MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures.- 5. 2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.- 6. Adaptive Task Migration Policies for Thermal Control in MPSoCs.- 7. A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning.- 8. A Scalable Bandwidth Aware Architecture for Connected Component Labelling.- 9. The SATURN Approach to SysML-based HW/SW Codesign.- 10. Mapping Embedded Applications on MPSoC - The MNEMEE approach.- 11. The MOSART Mapping Optimisation for Scalable Multi-core ARchiTecture.- 12. XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation.- 13. Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing.- 14. SUT-RNS Forward and Reverse Converters.- 15. Off-Chip SDRAM Access Through Spidergon STNoC.- 16. Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore.- 17. FPGA Startup through Sequential Partial and Dynamic Reconfiguration.- 18. Two Dimensional Dynamic Multigrained Reconfigurable Hardware.- 19. System Level Design for Embedded Reconfigurable Systems using MORPHEUS Platform.- 20. New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems through Dynamic and Partial Reconfiguration: The RAMPSoC Approach.
1. Intelligent NOC Hotspot Prediction.- 2. Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model.- 3. Trust Management Through Hardware Means: Design Concerns and Optimizations.- 4. MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures.- 5. 2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.- 6. Adaptive Task Migration Policies for Thermal Control in MPSoCs.- 7. A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning.- 8. A Scalable Bandwidth Aware Architecture for Connected Component Labelling.- 9. The SATURN Approach to SysML-based HW/SW Codesign.- 10. Mapping Embedded Applications on MPSoC - The MNEMEE approach.- 11. The MOSART Mapping Optimisation for Scalable Multi-core ARchiTecture.- 12. XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation.- 13. Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing.- 14. SUT-RNS Forward and Reverse Converters.- 15. Off-Chip SDRAM Access Through Spidergon STNoC.- 16. Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore.- 17. FPGA Startup through Sequential Partial and Dynamic Reconfiguration.- 18. Two Dimensional Dynamic Multigrained Reconfigurable Hardware.- 19. System Level Design for Embedded Reconfigurable Systems using MORPHEUS Platform.- 20. New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems through Dynamic and Partial Reconfiguration: The RAMPSoC Approach.
Es gelten unsere Allgemeinen Geschäftsbedingungen: www.buecher.de/agb
Impressum
www.buecher.de ist ein Shop der buecher.de GmbH & Co. KG Bürgermeister-Wegele-Str. 12, 86167 Augsburg Amtsgericht Augsburg HRA 13309
