This book discusses practical implementation architectures for modern error-correcting codes, providing details for every functional block as well as the overall decoder architecture. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. Many examples and case studies are included. More importantly, the advantages and drawbacks of different implementation approaches and architectures are compared. Thus, this book makes an ideal reference for system and hardware designers and graduate-level courses on VLSI design and error-correcting coding.
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