Ulrich Golze

VLSI Chip Design with the Hardware Description Language VERILOG (eBook, PDF)

An Introduction Based on a Large RISC Processor Design

• Format: PDF

Produktbeschreibung

This book introduces to modern design of large chips. A powerful RISC processor in the range of a SPARC is apecified in a hardware description language (HDL), it is developed hierarchically and is finally sent as a gate model to the silicon vendor LSI Logic for production. The resulting processor on a semi-custom gate-array chip with more than 50.000 used gates and an efficiency of up to 40 MIPS is tested on an automatic test equipment and a testboard. The book also introduces thoroughly to the HDL VERILOG. The included disk contains more than 40 small and medium sized executable VERILOG examples, the large processor models and the VERILOG simulator VeriWell running on PC or SPARC.

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Produktdetails

• Verlag: Springer Berlin Heidelberg
• Seitenzahl: 360
• Erscheinungstermin: 11. November 2013
• Englisch
• ISBN-13: 9783642610011
• Artikelnr.: 53137019

Autorenporträt

Prof. Dr. Ulrich Golze ist Professor für den Entwurf integrierter Schaltungen an der TU Braunschweig.

Inhaltsangabe

Design of VLSI Circuits.- Design of VLSI Circuits.- RISC Architectures.- RISC Architectures.- Short Introduction to VERILOG.- Short Introduction to VERILOG.- External Specification of Behavior.- External Specification of Behavior.- Internal Specification of Coarse Structure.- Internal Specification of Coarse Structure.- Pipeline of the Coarse Structure Model.- Pipeline of the Coarse Structure Model.- Synthesis of Gate Model.- Synthesis of Gate Model.- Testing, Testability, Tester, and Testboard.- Testing, Testability, Tester, and Testboard.- Summary and Prospect.- Summary and Prospect.- HDL Models for Circuits and Architectures.- HDL Modeling with VERILOG.