Stephen W. Director, Wojciech Maly, Andrzej J. Strojwas

VLSI Design for Manufacturing: Yield Enhancement (eBook, PDF)

• Format: PDF

Produktbeschreibung

One of the keys to success in the IC industry is getting a new product to market in a timely fashion and being able to produce that product with sufficient yield to be profitable. There are two ways to increase yield: by improving the control of the manufacturing process and by designing the process and the circuits in such a way as to minimize the effect of the inherent variations of the process on performance. The latter is typically referred to as "design for manufacture" or "statistical design". As device sizes continue to shrink, the effects of the inherent fluctuations in the IC fabrication process will have an even more obvious effect on circuit performance. And design for manufacture will increase in importance. We have been working in the area of statistically based computer aided design for more than 13 years. During the last decade we have been working with each other, and individually with our students, to develop methods and CAD tools that can be used to improve yield during the design and manufacturing phases of IC realization. This effort has resulted in a large number of publications that have appeared in a variety of journals and conference proceedings. Thus our motivation in writing this book is to put, in one place, a description of our approach to IC yield enhancement. While the work that is contained in this book has appeared in the open literature, we have attempted to use a consistent notation throughout this book.

---

Dieser Download kann aus rechtlichen Gründen nur mit Rechnungsadresse in A, B, BG, CY, CZ, D, DK, EW, E, FIN, F, GR, HR, H, IRL, I, LT, L, LR, M, NL, PL, P, R, S, SLO, SK ausgeliefert werden.

Produktdetails

• Verlag: Springer New York
• Seitenzahl: 292
• Erscheinungstermin: 6. Dezember 2012
• Englisch
• ISBN-13: 9781461315216
• Artikelnr.: 44181288

Inhaltsangabe

1. Yield Estimation and Prediction.- 1.1. Introduction.- 1.2. The VLSI Fabrication Process.- 1.3. Disturbances in the IC Manufacturing Process.- 1.4. Measures of Process Efficiency.- 1.5. Discussion.- 1.6. Overview of the Sequel.- 2. Parametric Yield Maximization.- 2.1. Introduction.- 2.2. Design Centering and Worst Case Design with Arbitrary Statistical Distributions.- 2.3. Example of Worst Case Design.- 2.4. A Dimension Reduction Procedure.- 2.5. Fabrication Based Statistical Design of Monolithic IC's.- 3. Statistical Process Simulation.- 3.1. Introduction.- 3.2. Statistical Process Simulation.- 3.3. Tuning of Process Simulator with PROMETHEUS.- 3.4. The Process Engineer's Workbench.- 4. Statistical Analysis.- 4.1. Statistical Timing Simulation.- 4.2. An Improved Worst-Case Analysis Procedure.- 4.3. Optimal Device and Cell Design Using FABRICS.- 5. Functional Yield.- 5.1. Introduction.- 5.2. Basic Characteristics of Spot Defects.- 5.3. Yield Modeling Using Virtual Layout.- 5.4. Monte Carlo Approach to Functional Yield Prediction.- 5.5. Yield Computations for VLSI Cell.- 6. Computer-Aided Manufacturing.- 6.1. Motivation.- 6.2. Overview of the CMU-CAM System.- 6.3. Statistical Process Control: The Unified Framework.- 6.4. CMU-CAM Software System.- 6.5. Computational Examples.- 6.6. Conclusions.- References.