VLSI-SoC: Design Trends (eBook, PDF)

28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers
Redaktion: Calimera, Andrea; Reis, Ricardo; Kvatinsky, Shahar; Korgaonkar, Kunal; Gaillardon, Pierre-Emmanuel

• Format: PDF

Produktbeschreibung

This book contains extended and revised versions of the best papers presented at the 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, held in Salt Lake City, UT, USA, in October 2020.*

The 16 full papers included in this volume were carefully reviewed and selected from the 38 papers (out of 74 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like low-power design of RF, analog and mixed-signal circuits, EDA tools for the synthesis and verification of heterogenous SoCs, accelerators for cryptography and deep learning and on-chip Interconnection system, reliability and testing, and integration of 3D-ICs.

*The conference was held virtually.

---

Dieser Download kann aus rechtlichen Gründen nur mit Rechnungsadresse in A, B, BG, CY, CZ, D, DK, EW, E, FIN, F, GR, HR, H, IRL, I, LT, L, LR, M, NL, PL, P, R, S, SLO, SK ausgeliefert werden.

Produktdetails

• Verlag: Springer International Publishing
• Seitenzahl: 364
• Erscheinungstermin: 14. Juli 2021
• Englisch
• ISBN-13: 9783030816414
• Artikelnr.: 62245602

Inhaltsangabe

Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22nm FDSOI.- A 125 pJ/b Mixed-Mode MCMC MIMO Detector with Relaxed DSP.- Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring.- Fully-Autonomous SoC Synthesis using Customizable Cell-Based Analog and Mixed-signal Circuits Generation.- Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform.- SAT-Based Mapping of Data-Flow Graph onto Coarse-Grained Reconfigurable Array.- Learning Based Timing Closure on Relative Timed Design.- Multilevel Signalling for High-Speed Chiplet-to-Chiplet Communication.- From Informal Specifications to an ABV Framework for Industrial Firmware Verification.- Modular Functional Testing: Targeting the Small Embedded Memories in GPUs.- RAT: A Lightweight Architecture Independent System-level Soft Error Mitigation Technique.- SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption.- 3D Nanofabric: Layout Challenges and Solutions for Ultra-Scaled Logic Designs.- 3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.- Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics.- A Technology Backward-Compatible Compilation Flow for Processing-In-Memory.