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Cyclic Redundancy Check is the most powerful of the redundancy checking techniques.CRC continues to be best suited for network based applications, which are characterized by medium level noise. In this book, The aim is designing and implementing a CRC circuit architecture , which is reconfigurable in terms of CRC polynomial and message size using FPGA. It is best suited for communication between PCs ,where error detection and retransmission is of main concern rather than error correction.The FPGA serves as the control unit to facilitate the communication between the PCs. Frequency division is performed to match the speed between the computer and the FPGA.The implementation is done up to 32-bit CRC polynomial. Appropriate CRC selection is done using a look up table depending on the applicationThe resulting circuit is of reduced cost, improved speed and significant capabilities to operate an extensive range of CRC polynomials and message width instead of just one.