Andere Kunden interessierten sich auch für
![VHDL based design of energy efficient MIL-STD 1553B Manchester Decoder]( "VHDL based design of energy efficient MIL-STD 1553B Manchester Decoder")
VHDL based design of energy efficient MIL-STD 1553B Manchester Decoder23,99 €![Majority Logic Detector/Decoder with prior error detection]( "Majority Logic Detector/Decoder with prior error detection")
Majority Logic Detector/Decoder with prior error detection26,99 €![Low Power Asynchronous Viterbi Decoder]( "Low Power Asynchronous Viterbi Decoder")
Low Power Asynchronous Viterbi Decoder36,99 €![Optical CDMA Spectral Encoder /Decoder]( "Optical CDMA Spectral Encoder /Decoder")
Optical CDMA Spectral Encoder /Decoder26,99 €![Adaptive K-Best Sphere Decoder for DVB Systems & Cooperative Networks]( "Adaptive K-Best Sphere Decoder for DVB Systems & Cooperative Networks")
Adaptive K-Best Sphere Decoder for DVB Systems & Cooperative Networks32,99 €![A Simulation Tool for LDPC Encoder-Decoder]( "A Simulation Tool for LDPC Encoder-Decoder")
A Simulation Tool for LDPC Encoder-Decoder23,99 €![Design of Reconfigurable VLIW Processor]( "Design of Reconfigurable VLIW Processor")
Design of Reconfigurable VLIW Processor36,99 €
Decoder design consists of choosing the optimal performance circuit style, providing flexibility in configuration of different sizes, sizing of transistors, adding buffers and consideration of fan outs. In this work, high speed reconfigurable decoders of different styles are analyzed for different loads of memory blocks. The power dissipation, delay, frequency & Vdd of various logic styles are analyzed. Evaluation of delay is done by changing Vdd, Speed is improved and power dissipation is minimized by a sizing technique. The memory system plays crucial role in determining optimum performance, power, speed and cost of the simple to complex machines. To improve the access time in memory system, there is requirement of configurable logic block which can be used to select rows and columns of partitioned memory blocks. In a memory for accessing and locating any random data, address decoders are used. The decoder block is contributing in access time and power consumption of memories. In this work, a reconfigurable decoder is proposed to select fewer word lines and to avoid large word line / bit line capacitance.