A Fully Integrated Phase Locked Loop at 61.44 GHz for High-Speed Wireless LANs
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In this dissertation, a fully integrated 61.44 GHz PLL was designed and measured. Capacitor multiplication was used to enable the integration of the loop filter on chip and the effect of the capacitor multiplier on the total PLL phase noise performance was quantified and evaluated. Additionally, the effect of the HBT transistor parasitics on the negative resistance of Colpitts oscillators was analyzed and the negative resistance equation, which is available in literature, was extended. Furthermore, a design methodology for choosing the load impedance of Colpitts oscillators was explained. More...
In this dissertation, a fully integrated 61.44 GHz PLL was designed and measured. Capacitor multiplication was used to enable the integration of the loop filter on chip and the effect of the capacitor multiplier on the total PLL phase noise performance was quantified and evaluated. Additionally, the effect of the HBT transistor parasitics on the negative resistance of Colpitts oscillators was analyzed and the negative resistance equation, which is available in literature, was extended. Furthermore, a design methodology for choosing the load impedance of Colpitts oscillators was explained. Moreover, the frequency limits of the operation of HBT cross coupled oscillators at high frequencies were studied and an extended expression of the negative conductance of the oscillator and an expression for the frequency at which the conductance of the oscillator changes its value from negative to positive, were derived.
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