Design and Implementation of a Novel Multilevel Inverter - Kumar, B. Jagadish
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A novel multilevel dc¿ac inverter is proposed. The proposed multilevel inverter generates seven-level ac output voltage with the appropriate gate signals¿ design. Also, the low-pass ¿lter is used to reduce the total harmonic distortion of the sinusoidal output voltage. The switching losses and the voltage stress of power devices can be reduced in the proposed multilevel inverter. The operating principles of the proposed inverter and the voltage balancing method of input capacitors are discussed. The multilevel inverter is controlled with sinusoidal pulse-width modulation (SPWM).

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Produktbeschreibung
A novel multilevel dc¿ac inverter is proposed. The proposed multilevel inverter generates seven-level ac output voltage with the appropriate gate signals¿ design. Also, the low-pass ¿lter is used to reduce the total harmonic distortion of the sinusoidal output voltage. The switching losses and the voltage stress of power devices can be reduced in the proposed multilevel inverter. The operating principles of the proposed inverter and the voltage balancing method of input capacitors are discussed. The multilevel inverter is controlled with sinusoidal pulse-width modulation (SPWM).
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Autorenporträt
Dr. B. Jagadish Kumar was born in India. He received the B. Tech. degree in Electrical and Electronics Engineering, M.Tech degree in Power & Industrial Drives and the Ph.D. degree in Electrical & Electronics Engineering (Power Electronics) from JNTU Hyderabad.