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Model checking is a verification method developed to
test finite-state systems (e.g., communication
protocols, hardware circuits) against properties
expressed as formulas in temporal logic. The method
has proved successful in finding design flaws in many
real-life applications. Nevertheless,
models especially of software systems often tend to
have unbounded number of states. Traditionally,
verifying such systems using model checkers requires
first abstracting the systems into finite-state
models. We introduce a unified, automata-based
representation for infinite-state systems and linear
temporal logic properties, and describe a
model-checking technique for such specifications. We
exploit constraint solving and logic programming to
implement an efficient and robust infrastructure for
our model checker, and apply this implementation to
analyze vulnerabilities of computer systems and
configurations.
test finite-state systems (e.g., communication
protocols, hardware circuits) against properties
expressed as formulas in temporal logic. The method
has proved successful in finding design flaws in many
real-life applications. Nevertheless,
models especially of software systems often tend to
have unbounded number of states. Traditionally,
verifying such systems using model checkers requires
first abstracting the systems into finite-state
models. We introduce a unified, automata-based
representation for infinite-state systems and linear
temporal logic properties, and describe a
model-checking technique for such specifications. We
exploit constraint solving and logic programming to
implement an efficient and robust infrastructure for
our model checker, and apply this implementation to
analyze vulnerabilities of computer systems and
configurations.