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The material provides the reader with an understanding of the features and functions typically found on HSS devices. It explains how these HSS devices are used in protocol applications and the analysis which must be performed to use such HSS devices. The book is an assimilation of various topics with a focus on what chip designers need to understand in order to design chips using HSS cores.
The reader is first introduced to the basic concepts and the resulting features and functions typical of HSS devices. HSS devices are used in the context of a protocol application. The reader is then introduced to the basic concepts used by protocols, and overviews are provided for several protocol standards in which HSS devices are commonly used. Additional chapters describe the features, functions, and considerations associated with designing and analyzing a reference clock distribution network, as well as testing HSS hardware, analyzing signal integrity, and analyzing power consumption. Finally, any HSS core is not complete without a set of design kit models to facilitate integration within the chip design, and special topics uniquely related to design kits for HSS cores are discussed in the final chapter.
The simplest method of transferring data through the inputs or outputs of a silicon chip is to directly connect each bit of the datapath from one chip to the next chip. Once upon a time this was an acceptable approach. However, one aspect (and perhaps the only aspect) of chip design which has not changed during the career of the authors is Moore's Law, which has dictated substantial increases in the number of circuits that can be manufactured on a chip. The pin densities of chip packaging technologies have not increased at the same pace as has silicon density, and this has led to a prevalence of High Speed Serdes (HSS) devices as an inherent part of almost any chip design. HSS devices are the dominant form of input/output for many (if not most) high-integration chips, moving serial data between chips at speeds up to 10 Gbps and beyond. Chip designers with a background in digital logic design tend to view HSS devices as simply complex digital input/output cells. This view ignores the complexity associated with serially moving billions of bits of data per second. At these data rates, the assumptions associated with digital signals break down and analog factors demand consideration. The chip designer who oversimplifies the problem does so at his or her own peril.
The reader is first introduced to the basic concepts and the resulting features and functions typical of HSS devices. HSS devices are used in the context of a protocol application. The reader is then introduced to the basic concepts used by protocols, and overviews are provided for several protocol standards in which HSS devices are commonly used. Additional chapters describe the features, functions, and considerations associated with designing and analyzing a reference clock distribution network, as well as testing HSS hardware, analyzing signal integrity, and analyzing power consumption. Finally, any HSS core is not complete without a set of design kit models to facilitate integration within the chip design, and special topics uniquely related to design kits for HSS cores are discussed in the final chapter.
The simplest method of transferring data through the inputs or outputs of a silicon chip is to directly connect each bit of the datapath from one chip to the next chip. Once upon a time this was an acceptable approach. However, one aspect (and perhaps the only aspect) of chip design which has not changed during the career of the authors is Moore's Law, which has dictated substantial increases in the number of circuits that can be manufactured on a chip. The pin densities of chip packaging technologies have not increased at the same pace as has silicon density, and this has led to a prevalence of High Speed Serdes (HSS) devices as an inherent part of almost any chip design. HSS devices are the dominant form of input/output for many (if not most) high-integration chips, moving serial data between chips at speeds up to 10 Gbps and beyond. Chip designers with a background in digital logic design tend to view HSS devices as simply complex digital input/output cells. This view ignores the complexity associated with serially moving billions of bits of data per second. At these data rates, the assumptions associated with digital signals break down and analog factors demand consideration. The chip designer who oversimplifies the problem does so at his or her own peril.