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  • Broschiertes Buch

A specially-designed, event-driven sensor processor architecture for the rare-event sensing applications is introduced by allowing the accuracy error, which is caused by the characteristics of the sensing applications. The conventional sensor processor performs the discrete-time based data sampling, data-quantization and utilizes the advanced time- quantization approach to reduce the energy consumption. Especially, for the rare-event applications, in which the event-to-event distance is very long, can be represented with the pre-defined event signal for a certain amount of signal range by the…mehr

Produktbeschreibung
A specially-designed, event-driven sensor processor architecture for the rare-event sensing applications is introduced by allowing the accuracy error, which is caused by the characteristics of the sensing applications. The conventional sensor processor performs the discrete-time based data sampling, data-quantization and utilizes the advanced time- quantization approach to reduce the energy consumption. Especially, for the rare-event applications, in which the event-to-event distance is very long, can be represented with the pre-defined event signal for a certain amount of signal range by the event type data of the signal shape and featured elapsed time range. The received analog signals for the specified time region are converted into the series of the atomic events by the signal-to-event con- verter (S2E) before the sensor data processing is performed. The signal-to-event conversion approach consumes additional power consumption, but the entire signal sampling rate can be reduced, which is more effective way to reduce the energy consumption. This book gives all details in RTL-level hardware design and MCU firmware implementation for event-driven sensor signal processing.
Autorenporträt
With over 14 years of industrial and academic experience in low-power robust embedded system design, he played a key role in successfully designing custom-designed applications processors with VLSI hardware accelerator and hardware resource-aware software optimization, especially for hardware/software tightly-coupled applications.