Advanced Signal Integrity for High-Speed Digital Designs (eBook, PDF)
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Advanced Signal Integrity for High-Speed Digital Designs (eBook, PDF)
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A synergistic approach to signal integrity for high-speed digital design This book is designed to provide contemporary readers with an understanding of the emerging high-speed signal integrity issues that are creating roadblocks in digital design. Written by the foremost experts on the subject, it leverages concepts and techniques from non-related fields such as applied physics and microwave engineering and applies them to high-speed digital design--creating the optimal combination between theory and practical applications. Following an introduction to the importance of signal integrity,…mehr
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- Produktdetails
- Verlag: John Wiley & Sons
- Seitenzahl: 688
- Erscheinungstermin: 6. April 2009
- Englisch
- ISBN-13: 9780470423882
- Artikelnr.: 37291946
- Verlag: John Wiley & Sons
- Seitenzahl: 688
- Erscheinungstermin: 6. April 2009
- Englisch
- ISBN-13: 9780470423882
- Artikelnr.: 37291946
- Herstellerkennzeichnung Die Herstellerinformationen sind derzeit nicht verfügbar.
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__ 269 6.4.2 Mathematical Limits 271 6.5 Fiber-Weave Effect 274 6.5.1 Physical Structure of an FR4 Dielectric and Dielectric Constant Variation 275 6.5.2 Mitigation 276 6.5.3 Modeling the Fiber-Weave Effect 277 6.6 Environmental Variation in Dielectric Behavior 279 6.6.1 Environmental Effects on Transmission-Line Performance 281 6.6.2 Mitigation 283 6.6.3 Modeling the Effect of Relative Humidity on an FR4 Dielectric 284 6.7 Transmission-Line Parameters for Lossy Dielectrics and Realistic Conductors 285 6.7.1 Equivalent Circuit Impedance and Propagation Constant 285 6.7.2 Telegrapher's Equations for Realistic Conductors and Lossy Dielectrics 291 References 292 Problems 292 7. Differential Signaling 297 7.1 Removal of Common-Mode Noise 299 7.2 Differential Crosstalk 300 7.3 Virtual Reference Plane 302 7.4 Propagation of Modal Voltages 303 7.5 Common Terminology 304 7.6 Drawbacks of Differential Signaling 305 7.6.1 Mode Conversion 305 7.6.2 Fiber-Weave Effect 310 Reference 313 Problems 313 8. Mathematical Requirements for Physical Channels 315 8.1 Frequency-Domain Effects in Time-Domain Simulations 316 8.1.1 Linear and Time Invariance 316 8.1.2 Time- and Frequency-Domain Equivalencies 317 8.1.3 Frequency Spectrum of a Digital Pulse 321 8.1.4 System Response 324 8.1.5 Single-Bit (Pulse) Response 327 8.2 Requirements for a Physical Channel 331 8.2.1 Causality 331 8.2.2 Passivity 340 8.2.3 Stability 343 References 345 Problems 345 9. Network Analysis for Digital Engineers 347 9.1 High-Frequency Voltage and Current Waves 349 9.1.1 Input Reflection into a Terminated Network 349 9.1.2 Input Impedance 353 9.2 Network Theory 354 9.2.1 Impedance Matrix 355 9.2.2 Scattering Matrix 358 9.2.3 ABCD Parameters 382 9.2.4 Cascading S-Parameters 390 9.2.5 Calibration and Deembedding 395 9.2.6 Changing the Reference Impedance 399 9.2.7 Multimode S-Parameters 400 9.3 Properties of Physical S-Parameters 406 9.3.1 Passivity 406 9.3.2 Reality 408 9.3.3 Causality 408 9.3.4 Subjective Examination of S-Parameters 410 References 413 Problems 413 10. Topics in High-Speed Channel Modeling 417 10.1 Creating a Physical Transmission-Line Model 418 10.1.1 Tabular Approach 418 10.1.2 Generating a Tabular Dielectric Model 419 10.1.3 Generating a Tabular Conductor Model 420 10.2 NonIdeal Return Paths 422 10.2.1 Path of Least Impedance 422 10.2.2 Transmission Line Routed Over a Gap in the Reference Plane 423 10.2.3 Summary 434 10.3 Vias 434 10.3.1 Via Resonance 434 10.3.2 Plane Radiation Losses 437 10.3.3 Parallel-Plate Waveguide 439 References 441 Problems 442 11. I/O Circuits and Models 443 11.1 I/O Design Considerations 444 11.2 Push-Pull Transmitters 446 11.2.1 Operation 446 11.2.2 Linear Models 448 11.2.3 Nonlinear Models 453 11.2.4 Advanced Design Considerations 455 11.3 CMOS receivers 459 11.3.1 Operation 459 11.3.2 Modeling 460 11.3.3 Advanced Design Considerations 460 11.4 ESD Protection Circuits 460 11.4.1 Operation 461 11.4.2 Modeling 461 11.4.3 Advanced Design Considerations 463 11.5 On-Chip Termination 463 11.5.1 Operation 463 11.5.2 Modeling 463 11.5.3 Advanced Design Considerations 464 11.6 Bergeron Diagrams 465 11.6.1 Theory and Method 470 11.6.2 Limitations 474 11.7 Open-Drain Transmitters 474 11.7.1 Operation 474 11.7.2 Modeling 476 11.7.3 Advanced Design Considerations 476 11.8 Differential Current-Mode Transmitters 479 11.8.1 Operation 479 11.8.2 Modeling 480 11.8.3 Advanced Design Considerations 480 11.9 Low-Swing and Differential Receivers 481 11.9.1 Operation 481 11.9.2 Modeling 482 11.9.3 Advanced Design Considerations 483 11.10 IBIS Models 483 11.10.1 Model Structure and Development Process 483 11.10.2 Generating Model Data 485 11.10.3 Differential I/O Models 488 11.10.4 Example of an IBIS File 490 11.11 Summary 492 References 492 Problems 494 12. Equalization 499 12.1 Analysis and Design Background 500 12.1.1 Maximum Data Transfer Capacity 500 12.1.2 Linear Time-Invariant Systems 502 12.1.3 Ideal Versus Practical Interconnects 506 12.1.4 Equalization Overview 511 12.2 Continuous-Time Linear Equalizers 513 12.2.1 Passive CTLEs 514 12.2.2 Active CTLEs 521 12.3 Discrete Linear Equalizers 522 12.3.1 Transmitter Equalization 525 12.3.2 Coefficient Selection 530 12.3.3 Receiver Equalization 535 12.3.4 Nonidealities in DLEs 536 12.3.5 Adaptive Equalization 536 12.4 Decision Feedback Equalization 540 12.5 Summary 542 References 545 Problems 546 13. Modeling and Budgeting of Timing Jitter and Noise 549 13.1 Eye Diagram 550 13.2 Bit Error Rate 552 13.2.1 Worst-Case Analysis 552 13.2.2 Bit Error Rate Analysis 555 13.3 Jitter Sources and Budgets 560 13.3.1 Jitter Types and Sources 561 13.3.2 System Jitter Budgets 568 13.4 Noise Sources and Budgets 572 13.4.1 Noise Sources 572 13.4.2 Noise Budgets 579 13.5 Peak Distortion Analysis Methods 583 13.5.1 Superposition and the Pulse Response 583 13.5.2 Worst-Case Bit Patterns and Data Eyes 585 13.5.3 Peak Distortion Analysis Including Crosstalk 594 13.5.4 Limitations 598 13.6 Summary 599 References 599 Problems 600 14. System Analysis Using Response Surface Modeling 605 14.1 Model Design Considerations 606 14.2 Case Study: 10-Gb/s Differential PCB Interface 607 14.3 RSM Construction by Least Squares Fitting 607 14.4 Measures of Fit 615 14.4.1 Residuals 615 14.4.2 Fit Coefficients 616 14.5 Significance Testing 618 14.5.1 Model Significance: The F-Test 618 14.5.2 Parameter Significance: Individual t-Tests 619 14.6 Confidence Intervals 621 14.7 Sensitivity Analysis and Design Optimization 623 14.8 Defect Rate Prediction Using Monte Carlo Simulation 628 14.9 Additional RSM Considerations 633 14.10 Summary 633 References 634 Problems 635 Appendix A: Useful Formulas Identities Units and Constants 637 Appendix B: Four-Port Conversions Between T- and S-Parameters 641 Appendix C: Critical Values of the F-Statistic 645 Appendix D: Critical Values of the T-Statistic 647 Appendix E: Causal Relationship Between Skin Effect Resistance and Internal Inductance for Rough Conductors 649 Appendix F: Spice Level 3 Model for 0.25
m MOSIS Process 653 Index 655
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__ 269 6.4.2 Mathematical Limits 271 6.5 Fiber-Weave Effect 274 6.5.1 Physical Structure of an FR4 Dielectric and Dielectric Constant Variation 275 6.5.2 Mitigation 276 6.5.3 Modeling the Fiber-Weave Effect 277 6.6 Environmental Variation in Dielectric Behavior 279 6.6.1 Environmental Effects on Transmission-Line Performance 281 6.6.2 Mitigation 283 6.6.3 Modeling the Effect of Relative Humidity on an FR4 Dielectric 284 6.7 Transmission-Line Parameters for Lossy Dielectrics and Realistic Conductors 285 6.7.1 Equivalent Circuit Impedance and Propagation Constant 285 6.7.2 Telegrapher's Equations for Realistic Conductors and Lossy Dielectrics 291 References 292 Problems 292 7. Differential Signaling 297 7.1 Removal of Common-Mode Noise 299 7.2 Differential Crosstalk 300 7.3 Virtual Reference Plane 302 7.4 Propagation of Modal Voltages 303 7.5 Common Terminology 304 7.6 Drawbacks of Differential Signaling 305 7.6.1 Mode Conversion 305 7.6.2 Fiber-Weave Effect 310 Reference 313 Problems 313 8. Mathematical Requirements for Physical Channels 315 8.1 Frequency-Domain Effects in Time-Domain Simulations 316 8.1.1 Linear and Time Invariance 316 8.1.2 Time- and Frequency-Domain Equivalencies 317 8.1.3 Frequency Spectrum of a Digital Pulse 321 8.1.4 System Response 324 8.1.5 Single-Bit (Pulse) Response 327 8.2 Requirements for a Physical Channel 331 8.2.1 Causality 331 8.2.2 Passivity 340 8.2.3 Stability 343 References 345 Problems 345 9. Network Analysis for Digital Engineers 347 9.1 High-Frequency Voltage and Current Waves 349 9.1.1 Input Reflection into a Terminated Network 349 9.1.2 Input Impedance 353 9.2 Network Theory 354 9.2.1 Impedance Matrix 355 9.2.2 Scattering Matrix 358 9.2.3 ABCD Parameters 382 9.2.4 Cascading S-Parameters 390 9.2.5 Calibration and Deembedding 395 9.2.6 Changing the Reference Impedance 399 9.2.7 Multimode S-Parameters 400 9.3 Properties of Physical S-Parameters 406 9.3.1 Passivity 406 9.3.2 Reality 408 9.3.3 Causality 408 9.3.4 Subjective Examination of S-Parameters 410 References 413 Problems 413 10. Topics in High-Speed Channel Modeling 417 10.1 Creating a Physical Transmission-Line Model 418 10.1.1 Tabular Approach 418 10.1.2 Generating a Tabular Dielectric Model 419 10.1.3 Generating a Tabular Conductor Model 420 10.2 NonIdeal Return Paths 422 10.2.1 Path of Least Impedance 422 10.2.2 Transmission Line Routed Over a Gap in the Reference Plane 423 10.2.3 Summary 434 10.3 Vias 434 10.3.1 Via Resonance 434 10.3.2 Plane Radiation Losses 437 10.3.3 Parallel-Plate Waveguide 439 References 441 Problems 442 11. I/O Circuits and Models 443 11.1 I/O Design Considerations 444 11.2 Push-Pull Transmitters 446 11.2.1 Operation 446 11.2.2 Linear Models 448 11.2.3 Nonlinear Models 453 11.2.4 Advanced Design Considerations 455 11.3 CMOS receivers 459 11.3.1 Operation 459 11.3.2 Modeling 460 11.3.3 Advanced Design Considerations 460 11.4 ESD Protection Circuits 460 11.4.1 Operation 461 11.4.2 Modeling 461 11.4.3 Advanced Design Considerations 463 11.5 On-Chip Termination 463 11.5.1 Operation 463 11.5.2 Modeling 463 11.5.3 Advanced Design Considerations 464 11.6 Bergeron Diagrams 465 11.6.1 Theory and Method 470 11.6.2 Limitations 474 11.7 Open-Drain Transmitters 474 11.7.1 Operation 474 11.7.2 Modeling 476 11.7.3 Advanced Design Considerations 476 11.8 Differential Current-Mode Transmitters 479 11.8.1 Operation 479 11.8.2 Modeling 480 11.8.3 Advanced Design Considerations 480 11.9 Low-Swing and Differential Receivers 481 11.9.1 Operation 481 11.9.2 Modeling 482 11.9.3 Advanced Design Considerations 483 11.10 IBIS Models 483 11.10.1 Model Structure and Development Process 483 11.10.2 Generating Model Data 485 11.10.3 Differential I/O Models 488 11.10.4 Example of an IBIS File 490 11.11 Summary 492 References 492 Problems 494 12. Equalization 499 12.1 Analysis and Design Background 500 12.1.1 Maximum Data Transfer Capacity 500 12.1.2 Linear Time-Invariant Systems 502 12.1.3 Ideal Versus Practical Interconnects 506 12.1.4 Equalization Overview 511 12.2 Continuous-Time Linear Equalizers 513 12.2.1 Passive CTLEs 514 12.2.2 Active CTLEs 521 12.3 Discrete Linear Equalizers 522 12.3.1 Transmitter Equalization 525 12.3.2 Coefficient Selection 530 12.3.3 Receiver Equalization 535 12.3.4 Nonidealities in DLEs 536 12.3.5 Adaptive Equalization 536 12.4 Decision Feedback Equalization 540 12.5 Summary 542 References 545 Problems 546 13. Modeling and Budgeting of Timing Jitter and Noise 549 13.1 Eye Diagram 550 13.2 Bit Error Rate 552 13.2.1 Worst-Case Analysis 552 13.2.2 Bit Error Rate Analysis 555 13.3 Jitter Sources and Budgets 560 13.3.1 Jitter Types and Sources 561 13.3.2 System Jitter Budgets 568 13.4 Noise Sources and Budgets 572 13.4.1 Noise Sources 572 13.4.2 Noise Budgets 579 13.5 Peak Distortion Analysis Methods 583 13.5.1 Superposition and the Pulse Response 583 13.5.2 Worst-Case Bit Patterns and Data Eyes 585 13.5.3 Peak Distortion Analysis Including Crosstalk 594 13.5.4 Limitations 598 13.6 Summary 599 References 599 Problems 600 14. System Analysis Using Response Surface Modeling 605 14.1 Model Design Considerations 606 14.2 Case Study: 10-Gb/s Differential PCB Interface 607 14.3 RSM Construction by Least Squares Fitting 607 14.4 Measures of Fit 615 14.4.1 Residuals 615 14.4.2 Fit Coefficients 616 14.5 Significance Testing 618 14.5.1 Model Significance: The F-Test 618 14.5.2 Parameter Significance: Individual t-Tests 619 14.6 Confidence Intervals 621 14.7 Sensitivity Analysis and Design Optimization 623 14.8 Defect Rate Prediction Using Monte Carlo Simulation 628 14.9 Additional RSM Considerations 633 14.10 Summary 633 References 634 Problems 635 Appendix A: Useful Formulas Identities Units and Constants 637 Appendix B: Four-Port Conversions Between T- and S-Parameters 641 Appendix C: Critical Values of the F-Statistic 645 Appendix D: Critical Values of the T-Statistic 647 Appendix E: Causal Relationship Between Skin Effect Resistance and Internal Inductance for Rough Conductors 649 Appendix F: Spice Level 3 Model for 0.25
m MOSIS Process 653 Index 655