Formal Semantics and Verification Of Use Case Maps
An early stages Validation and Verification Approach
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This book proposes a novel methodology combining the semi-formal scenario-based Use Case Maps (UCM) language with formal techniques to help comprehend, validate and verify requirements. Use Case Maps (UCM), part of the ITU-T standard User Requirements Notation (URN) Z.151, allows for the description of functional requirements and high-level designs at early stages of the development process. The book proposes a rigorous formal semantics for Use Case Maps based on Abstract State Machines (ASM) formalism. The resulting semantics are expressed in AsmL, an advanced ASM-based executable specificati...
This book proposes a novel methodology combining the semi-formal scenario-based Use Case Maps (UCM) language with formal techniques to help comprehend, validate and verify requirements. Use Case Maps (UCM), part of the ITU-T standard User Requirements Notation (URN) Z.151, allows for the description of functional requirements and high-level designs at early stages of the development process. The book proposes a rigorous formal semantics for Use Case Maps based on Abstract State Machines (ASM) formalism. The resulting semantics are expressed in AsmL, an advanced ASM-based executable specification language. Furthermore, the Use Case Maps language is extended to cover timing constraints. A potential timed version of UCM (called Timed UCM) is formalized using Clocked Transition Systems (CTS) and Timed Automata (TA). In addition, the book proposed a novel UCM-based property pattern system that combines qualitative, real-time and architectural properties into a single graphical representation. The resulting pattern system is mapped to popular temporal logics such as CTL, TCTL and ArTCTL (Architectural real-time temporal logic), which extends TCTL with architectural scopes.
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