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This Book introduces a new architecture design for Direct Digital Frequency Synthesizer, the design is developed using top-down design flow from behavioral modeling down to the implementation process. The proposed architecture is intended for use in spread spectrum such as, frequency hopping transceiver and any other digital transceiver and aims to reduce the frequency switching time of the synthesizer and reduce power consumption of synthesizer compared to conventional designs. In order to avoid the high power consumption, no ROM is used but piecewise linear approximation is employed. The proposed architecture has been designed, simulated and synthesized using(XC4010xl) XILINX FPGA,with 3.3v supply voltage. The power consumption is 0.396 W at 100MHz clock frequency. The Spurious-Free Dynamic Range (SFDR) is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz. This book will include an introduction to the basic DDFS architecture and explain the modification added to the conventional DDFS to improve its performance. Also it explains the types of frequency synthesizer in modern transceivers.