Fighting Back the von Neumann Bottleneck with Small- and Large-Scale Vector Microprocessors - Cavalcante, Matheus
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In his seminal Turing Award Lecture, Backus discussed the issues stemming from the word-at-a-time style of programming inherited from the von Neumann computer. More than forty years later, computer architects must be creative to amortize the von Neumann Bottleneck (VNB) associated with fetching and decoding instructions which only keep the datapath busy for a very short period of time. In particular, vector processors promise to be one of the most efficient architectures to tackle the VNB, by amortizing the energy overhead of instruction fetching and decoding over several chunks of data. This…mehr

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Produktbeschreibung
In his seminal Turing Award Lecture, Backus discussed the issues stemming from the word-at-a-time style of programming inherited from the von Neumann computer. More than forty years later, computer architects must be creative to amortize the von Neumann Bottleneck (VNB) associated with fetching and decoding instructions which only keep the datapath busy for a very short period of time. In particular, vector processors promise to be one of the most efficient architectures to tackle the VNB, by amortizing the energy overhead of instruction fetching and decoding over several chunks of data. This work explores vector processing as an option to build small and efficient processing elements for large-scale clusters of cores sharing access to tightly-coupled L1 memory
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Autorenporträt
Matheus de Araújo Cavalcante was born the 6th November, 1995 in Campina Grande, Paraíba, Brazil. He received the M.Sc. degree in Integrated Electronic Systems from the Grenoble Institute of Technology (Phelma), Grenoble, France in 2018. Mr. Cavalcante successively joined the research group of Prof. Dr. Luca Benini at the Integrated Systems Laboratory (IIS) as a Ph.D. candidate. His research interests include high-performance computing systems, with particular interest in vector processors and manycore systems. He furthermore works in architectural co-optimization with emerging VLSI technologies, such as two-and-a-half and three-dimensional integrated circuits.