Andere Kunden interessierten sich auch für
![Computer-Aided Design Techniques for Low Power Sequential Logic Circuits]( "Computer-Aided Design Techniques for Low Power Sequential Logic Circuits")
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits116,99 €![Hierarchical Modeling for VLSI Circuit Testing]( "Hierarchical Modeling for VLSI Circuit Testing")
Hierarchical Modeling for VLSI Circuit Testing81,99 €![Neural Models and Algorithms for Digital Testing]( "Neural Models and Algorithms for Digital Testing")
Neural Models and Algorithms for Digital Testing81,99 €![High Frequency Continuous Time Filters in Digital CMOS Processes]( "High Frequency Continuous Time Filters in Digital CMOS Processes")
High Frequency Continuous Time Filters in Digital CMOS Processes77,99 €![Optimal VLSI Architectural Synthesis]( "Optimal VLSI Architectural Synthesis")
Optimal VLSI Architectural Synthesis121,99 €![IDDQ Testing of VLSI Circuits]( "IDDQ Testing of VLSI Circuits")
IDDQ Testing of VLSI Circuits81,99 €![Multi-Threshold CMOS Digital Circuits]( "Multi-Threshold CMOS Digital Circuits")
Multi-Threshold CMOS Digital Circuits77,99 €
In the last few years CMOS technology has become increas ingly dominant for realizing Very Large Scale Integrated (VLSI) circuits. The popularity of this technology is due to its high den sity and low power requirement. The ability to realize very com plex circuits on a single chip has brought about a revolution in the world of electronics and computers. However, the rapid advance ments in this area pose many new problems in the area of testing. Testing has become a very time-consuming process. In order to ease the burden of testing, many schemes for designing the circuit for improved testability have been presented. These design for testability techniques have begun to catch the attention of chip manufacturers. The trend is towards placing increased emphasis on these techniques. Another byproduct of the increase in the complexity of chips is their higher susceptibility to faults. In order to take care of this problem, we need to build fault-tolerant systems. The area of fault-tolerant computing has steadily gained in importance. Today many universities offer courses in the areas of digital system testing and fault-tolerant computing. Due to the impor tance of CMOS technology, a significant portion of these courses may be devoted to CMOS testing. This book has been written as a reference text for such courses offered at the senior or graduate level. Familiarity with logic design and switching theory is assumed. The book should also prove to be useful to professionals working in the semiconductor industry.
Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.
Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.