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In this project, Verilog HDL is used for the implementation due to its compatibility with pure digital hardware like FPGA's. The Digital PLL is simulated and verified on FPGA to experience its advantages. The circuit comprises of a phase detector, loop filter, Numerically Controlled Oscillator (NCO), and two clock dividers. The circuit was stabilized to produce the frequency in the audio frequency range of 9.7 KHz. This agreed with the classical phase-locked loop model for the system. The stable long-term frequency clock was verified on the FPGA to generate the required locking frequency. The DC logic synthesis and a new synopsis low power flow was experimented for back annotation and to obtain the maximum possible operating frequency and area, timing and power estimation.