Andere Kunden interessierten sich auch für
![High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip]( "High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip")
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip74,99 €![Testing Chips with Mesh-Based Network-on-Chip]( "Testing Chips with Mesh-Based Network-on-Chip")
Testing Chips with Mesh-Based Network-on-Chip44,99 €![Exploration of fusion-based approach for building a robust CBIR system]( "Exploration of fusion-based approach for building a robust CBIR system")
Exploration of fusion-based approach for building a robust CBIR system36,99 €![An EMV (Chip & PIN) Case Study]( "An EMV (Chip & PIN) Case Study")
An EMV (Chip & PIN) Case Study24,99 €![MEMORY HIERARCHY DESIGN FOR CHIP MULTIPROCESSORS]( "MEMORY HIERARCHY DESIGN FOR CHIP MULTIPROCESSORS")
MEMORY HIERARCHY DESIGN FOR CHIP MULTIPROCESSORS38,99 €![VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design]( "VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design")
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design37,99 €![Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures]( "Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures")
Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures74,99 €
About the Book: The goal of this text is to help students, researchers and academicians, who are working in the field of CAD for VLSI. Network-on-Chip(NoC) has been recently developed as an on-chip communication solution for System-on-Chip(SoC) design. This paradigm supports various communication resources at a time and overcomes the limitations of bus-based System. Design space exploration methodology at system level reduces the time-to-market pressure of the large and complex systems. On the other hand, design space exploration at system level is a combinatorial optimization problem. So, multi-objective Genetic Algorithm has been considered as an optimization tool for the design space exploration task. This book provides detailed methodology/algorithms to explore the design space of NoC at System Level using Genetic Algorithm. This book is the outcome of my PhD work. I hope this book will help all stake holders for extensive research in the field of NoC at System level.