Guide to RISC Processors - Dandamudi, Sivarama P.
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- Details RISC design principles as well as explains the differences between this and other designs
- Helps readers acquire hands-on assembly language programming experience
Recently, there has been a trend toward processors based on the RISC (Reduced Instruction Set Computer) design. This is an accessible and all-encompassing compendium on RISC processors, introducing five of them: MIPS, SPARC, PowerPC, ARM, and Intel's 64-bit Itanium. Initial chapters explain differences between the CISC and RISC designs, and the core RISC design principles are clearly discussed. Later chapters provide…mehr

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Produktbeschreibung
- Details RISC design principles as well as explains the differences between this and other designs

- Helps readers acquire hands-on assembly language programming experience
Recently, there has been a trend toward processors based on the RISC (Reduced Instruction Set Computer) design. This is an accessible and all-encompassing compendium on RISC processors, introducing five of them: MIPS, SPARC, PowerPC, ARM, and Intel's 64-bit Itanium. Initial chapters explain differences between the CISC and RISC designs, and the core RISC design principles are clearly discussed. Later chapters provide instruction on MIPS assembly language programming, so that readers can readily learn the concepts and principles introduced earlier. Professionals, programmers, and students in computer architecture and programming courses will find the guide an essential resource.
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Autorenporträt
Sivarama P. Dandamudi, Herzberg Laboratories, Ottawa, ON