Xilinx HDLC Supporting IP over SONET And Checking 16,32Bit CRC
XILINX HDLC and CRC Checking
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In the present work of Xilinx HDLC controller. HDLC operates at the data link layer of the OSI Model main focus of the is to understand the data link layer and develop a protocol which can offer its services to the layer above it i.e. is the network layer and the layer below it i.e. the physical layer. The function of this protocol controller is to perform a number of separate activities like physical addressing, to check for errors, flow control design of HDLC Controller and simulation design and implement a high performance. This will then be coded in a hardware description language (VHDL). ...
In the present work of Xilinx HDLC controller. HDLC operates at the data link layer of the OSI Model main focus of the is to understand the data link layer and develop a protocol which can offer its services to the layer above it i.e. is the network layer and the layer below it i.e. the physical layer. The function of this protocol controller is to perform a number of separate activities like physical addressing, to check for errors, flow control design of HDLC Controller and simulation design and implement a high performance. This will then be coded in a hardware description language (VHDL). The functioning of the coded design is to be simulated on simulation software (e.g. Model Sim.).After proper simulation, the design is to be synthesized and then translated to a structural architecture in terms of the components on the target FPGA device (Spartan 3) and the perform the post-translate simulation in order to ensure the proper functioning of the design after translation. After the successful simulation of the post-translate model the design is mapped to the existing slices of the FPGA and the post-map model simulated.The objective is to run the programmed FPGA high as possible.
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